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data sheet no. pd94705 ir3080 xphase tm vrd1 0 control ic with vc cvid & overtemp detect des cript ion the i r 30 80 control i c co mbined with an ir xphase tm pha s e i c provide s a fu ll featured an d flexible way to impleme n t a com p lete v rd 10 po we r solution. t he ?c o n trol ? ic provide s overall syste m co ntrol an d interfaces wit h any num be r of ?pha se i c s? which ea ch d r ive an d monitor a si n g le ph ase of a multipha se conve r ter. th e x phase tm architectu re result s in a po wer su pply th at is smalle r, less expe nsiv e, and e a si er to desig n whil e providin g hi gher effici en cy than conve n tional ap pro a ch es. the ir30 80 i s intend ed fo r desktop ap plicatio ns a n d in clu d e s the vccvid a nd vrhot functio n s requ ired for pro per system operation . feat ure s ? 6 bit vr10 co mpatible vid with 0.5% overall sy stem accuracy ? 1 to x phase s operatio n wit h matchin g p hase ics ? on-chip 7 0 0 ? vid pull-up resi stors with vid pull-up v o ltage inp u t ? programma bl e dynami c vid slew rate ? no di scha rge of output cap a citors du rin g dynamic vid step-d o wn (can be di sabl e d ) ? +/-30 0 mv diff erential rem o te sense ? programmabl e 150khz to 1mhz oscillat o r ? programma bl e vid offset and lo ad lin e output impe dan ce ? programma bl e softstart ? programma bl e hiccu p ove r -curre nt protecti on with delay to preve n t false trigge ring ? simplified powergoo d provides in dication of prope r o peratio n and avoids fal s e trigge rin g ? operates fro m 12v input wi th 9.1v un der-voltage l o ckout ? 6.8v/5ma bias re gulato r p r ovide s syste m referen c e voltage ? 1.2v @ 150m a vccvid li near reg u lat o r with full protection ? vccvid po wergo od with p r og ramm able delay gates conve r ter o p e r ation ? programma bl e conve r ter over-temp e rature detecti on and o u tpu t ? small thermal l y enhan ced 32l mlpq p a ckag e package pin out oc s e t 17 iin 18 v drp 19 fb 20 eaou t 21 bbf b 22 vbi as 23 vc c 24 lgn d 25 rm p o u t 26 h o t set 27 vr h o t 28 vi d 4 9 ro s c 15 vi d p g d 31 ss / d e l 29 vd ac 16 tr m 4 14 tr m 3 13 vosn s- 12 tr m 2 11 tr m 1 10 pw r g d 30 vi d 3 8 vi d 2 7 vi d 1 6 vi d 0 5 vi d 5 4 vi d p w r 3 v ccv id 2 vi d f b 1 vi d d e l 32 ir3080 control ic page 1 of 41 9 /30/04
ir3080 ordering inforamation dev i c e o r d e r qu antit y ir308 0mt r 3000 p e r reel * ir3080 m 100 pie c e stri ps * sa mp le s only absolute maximum ratings operating ju nction te mpe r ature?? ? ??..150 o c storage te m peratu r e ran ge?? ??? ??.-6 5 o c to 150 o c esd rating ???? ?? ???? ?? ??..hbm cl ass 1c jede c stan dard pin # pin name v ma x v mi n i sour ce i sink 1 v i d f b 2 0 v - 0 . 3 v 1 m a 1 m a 2 v c c v i d 2 0 v - 0 . 5 v 4 0 0 m a 5 0 m a 3 v i d p w r 2 0 v - 0 . 3 v 1 m a 4 0 0 m a 4 - 9 v i d 0 - 5 2 0 v - 0 . 3 v 1 0 m a 1 0 m a 10, 11, 13,14 trm1 -4 do n o t con n e ct do n o t con n ec t do not connec t do not connec t 1 2 v o s n s - 0 . 5 v - 0 . 5 v 1 0 m a 1 0 m a 1 5 r o s c 2 0 v - 0 . 5 v 1 m a 1 m a 1 6 v d a c 2 0 v - 0 . 3 v 1 m a 1 m a 1 7 o c s e t 2 0 v - 0 . 3 v 1 m a 1 m a 1 8 i i n 2 0 v - 0 . 3 v 1 m a 1 m a 1 9 v d r p 2 0 v - 0 . 3 v 5 m a 5 m a 2 0 f b 2 0 v - 0 . 3 v 1 m a 1 m a 2 1 e a o u t 1 0 v - 0 . 3 v 1 0 m a 2 0 m a 2 2 b b f b 2 0 v - 0 . 3 v 1 m a 1 m a 2 3 v b i a s 2 0 v - 0 . 3 v 1 m a 1 m a 2 4 v c c 2 0 v - 0 . 3 v 1 m a 5 0 m a 2 5 l g n d n / a n / a 5 0 m a 1 m a 2 6 r m p o u t 2 0 v - 0 . 3 v 1 m a 1 m a 2 7 h o t s e t 2 0 v - 0 . 3 v 1 m a 1 m a 2 8 v r h o t 2 0 v - 0 . 3 v 1 m a 5 0 m a 2 9 s s / d e l 2 0 v - 0 . 3 v 1 m a 1 m a 3 0 p w r g d 2 0 v - 0 . 3 v 1 m a 2 0 m a 3 1 v i d p g d 2 0 v - 0 . 3 v 1 m a 2 0 m a 3 2 v i d d e l 2 0 v - 0 . 3 v 1 m a 1 m a page 2 of 41 9 /30/04
ir3080 electrical specifications unle ss otherwise sp ecifie d, thes e spe c ification s appl y over: 9.5v ? v cc ? 14v, 2.0v ? vidpwr ? 5.5v and 0 o c ? t j ? 100 o c par a mete r t e s t con d i t i o n m i n t y p m a x u n i t vdac re fer e nce sys t em set-point ac c u rac y -0.3v ? vos n s- ? 0.3v, connec t fb t o eaout, meas ure v(eaout) ? v(vosns-) d e viation from table 1. applies to all vid codes. 0 . 5 % source curre n t r rosc = 41.9k ? 6 8 8 0 9 2 p a sink cu rrent r rosc = 41.9k ? 4 7 5 5 6 3 p a vid input thresh old 500 600 700 mv vid pull-up resi stors 500 700 1000 ? reg u lation detect co mpa r ator input offset - 5 0 5 m v regulation detec t to eaout delay 1 3 0 2 0 0 n s bbfb to fb bias current ratio 0 . 9 5 1 . 0 0 1 . 0 5 p a/ p a vid 11111x blankin g del a y measure time until pwrg d drive s low 800 ns vid step do wn d e tect blankin g tim e measure fro m vid inputs to eaout 1.7 p s vid down bb clamp volta ge percent of vdac voltage 70 75 80 % vid down bb clamp curre n t 3.5 6.2 12 ma error amplifier input offset voltage con n e c t fb to eaout, measure v(eaout ) ? v(dac). from table 1. applies to all vid code s an d -0.3v ? vosns- ? 0. 3v. note 2 - 3 4 8 m v fb bias cu rrent r rosc = 41.9k ? - 3 1 - 2 9 . 5 - 2 8 p a dc g a in note 1 90 100 105 db gain-b and wi dth produ ct note 1 4 7 mhz source curre n t 0.4 0.6 0.8 ma sink cu rrent 0.7 1.2 1.7 ma max voltage vbias?veaout (refe r en ced to vbias) 125 250 375 mv min voltage normal op era t ion or fault mode 30 100 150 mv vdrp buffer amplifier input offset voltage v(vdrp ) ? v(iin), 0.8v ? v(iin) ? 5.5v -8 0 8 mv input voltage rang e 0.8 5.5 v bandwi d th (-3db) note 1 1 6 mhz slew rate 10 v/ p s iin bias cu rrent -2.0 -0.75 0 p a page 3 of 41 9 /30/04
ir3080 par a mete r t e s t con d i t i o n m i n t y p m a x u n i t oscillator switchin g fre quen cy r rosc = 41.9k ? 2 5 5 3 0 0 3 4 5 k h z peak voltag e (5v typical, measured a s % of vbias) r rosc = 41.9k ? 7 0 7 1 7 4 % valley voltage (1v typical, measured a s % of vbias) r rosc = 41.9k ? 1 1 1 4 1 6 % vbias re gulator output voltag e -5ma ? i(vbias) ? 0 6.5 6.8 7.1 v curre n t limit -30 -15 -6 ma soft sta r t an d delay ss/del to fb input offset voltage with fb = 0v , adjus t v(ss/del) until eaout drive s high 0 . 8 5 1 . 3 1 . 5 v cha r ge cu rre nt 40 70 100 p a disch a rg e cu rre nt 4 6 9 p a cha r ge/ disch a rge cu rre nt ratio 1 0 1 1 . 5 1 3 p a/ p a cha r ge volta ge 3.7 4.0 4.2 v delay compa r ator t h re sh o l d relative to charg e voltag e 70 90 110 mv disch a rg e co mparator thre sh old 1 5 0 2 0 0 2 5 0 m v ov er-curren t compa r ato r input offset voltage -10 0 10 mv ocset bias current r rosc = 41.9k ? - 3 1 - 2 9 . 5 - 2 8 p a pwrgd ou tput output voltag e i(pwrgd) = 4ma 150 400 mv lea kag e cu rrent v(pwrg d) = 5.5v 0 10 p a vccvid reg u lator output voltag e -150 ma ? i(vccvid) ? 0 1.145 1.200 1.215 v dro pout volta ge i(vccvi d ) = -20ma 130 200 mv i ( v c c v i d ) = -150 m a 0 . 8 1 . 0 v curre n t l i m i t - 3 0 0 m a vidfb bias curre n t -225 -150 p a vccvid po w e rgood vccvid t h re shol d voltage relative to re gulated vccvid output voltage 1 . 0 5 1 . 1 0 1 . 1 3 v cha r ge cu rre nt 30 66 90 p a disch a rg e cu rre nt 4 7 11 ma cha r ge volta ge 3.7 4.0 4.2 v delay compa r ator t h re sh o l d relative to charg e voltag e 65 90 115 mv vidpgd out put voltage i(vidpgd) = 4ma 150 400 mv vidpgd le a k ag e cu rrent v(vidpgd) = 5.5v 0 10 p a page 4 of 41 9 /30/04
ir3080 par a mete r t e s t con d i t i o n m i n t y p m a x u n i t vcc under - voltage loc kout start thre sho l d 8.6 9.1 9.6 v stop thre sho l d 8.4 8.9 9.4 v hysteresi s start ? stop 150 200 300 mv gener a l vcc sup p ly curre n t 8 11 14 ma vidpwr su p p ly current vid0-5 o pen, i(vccvid) = 0 400 550 1000 p a vosns- current -0.3v ? vos n s- ? 0.3v, all vid codes -5.5 -4.5 -3.5 ma vrho t com p arat or hotset bia s cu rr ent -2 -0.5 1 p a output voltag e i(vrhot) = 2 9 ma 300 400 mv vrho t lea kage current v(vrhot ) = 5.5v 0 10 p a thre sh old hy stere s i s t j ? 85 o c 3 6 1 0 o c m i n t y p m a x thre sh old vo ltage (incre asi ng te mperature ) t j ? 85 o c 4.73mv/ o c x t j + 1.176v 4.73mv/ o c x t j + 1.241v 4.73mv/ o c x t j + 1.356v v not e 1: gu a r antee d by de sign, but not tested in p r od uction not e 2 : vdac output is tri mmed to co m pen sate for e rro r amplifier input offsets errors page 5 of 41 9 /30/04
ir3080 pin des c ription pin# pin symbo l pin descri ption 1 vidfb feedb ack to the vccvi d regulat o r . con nect to the vccvid o u tpu t. 2 vccvid 1.2v/150ma reg u lator o u tput. can also drive extern al pass tran si stor to minimi ze on-chip p o we r dissipatio n 3 vidpwr powe r for vid pull-u p re si stors and v c cvid re gulat or 4-9 vid0-5 inputs to vid d to a conve r ter. on -chip 700 ohm p u ll-up re sisto r s to vidpwr pi n are in clud ed. 10, 11, 13,14 trm1 -4 used for p r e c ision p o st-pa c kage trimmi ng of the vdac voltage. do not ma ke any con n e c tion to these pin s . 12 vosns- remote se nse input. conn ect to gro und at the load. 15 rosc con n e c t a re sisto r to vosns- to progra m oscillator freque ncy an d fb, ocset, bbfb, and vdac bia s currents 16 vdac reg u lated vol t age pro g ram m ed by the vid inputs. current sen s ing and pwm operation a r e refere nced to this pin. co nne ct an external rc net work to vos n s- to program dynamic vid s l ew rate. 17 ocset program s the hiccup over-curre nt thre shold thro ugh an external re sisto r tied to vdac an d an internal curre n t source. ov er-cu r rent pro t ection can b e disa bled by con n e c ting th is pin to a dc voltage no greater than 6. 5v (do not flo a t this pin as improper operation will occur). 18 iin curre n t sense input from the phase ic(s). to en su re prop er o peration bia s to at least 25 0mv (don?t float this pin). 19 vdrp buffered iin signal. co nne ct an external rc n e two r k t o fb to program conve r ter output imped ance 20 fb inverting inpu t to the error amplifier. co nverter o u tpu t voltage is offset from the vdac voltag e throug h an external resi stor con n e c ted to the converter output voltage at the load an d an intern al curre n t sou r ce. 21 eaout output of the erro r amplifie r 22 bbfb input to the regulatio n det e ct co mpa r at or. con n e c t to conve r ter o u tput voltage and vdrp pin through resi sto r netwo rk to p r ogra m re cove ry from vid step-d o wn. con n e c t to ground to dia b l e body braki n g tm durin g transitio n to a lowe r vid co d e . 23 vbias 6.8v/5ma re gulated o u tpu t used a s a sys tem refe ren c e voltage for internal ci rcu i try and the pha s e ics 24 vcc powe r for internal circuitry 25 lgnd local gro und and ic su bst r ate co nne cti on 26 rmpo ut oscillator out put voltage. used by pha s e ics to pro g ram pha s e delay 27 hotset inverting inpu t to vrhot compa r ator. conne ct re sist or divide r fro m vbias to lgnd to prog ram v r hot thre sh old. diod e or thermi stor ma y be sub s tituted for lower resi sto r for en han ced/remot e temperat ure sen s in g. applying a voltage exce edin g approximatel y 7.5v disabl es the o sc ill ator for facto r y testing. 28 vrho t open colle ct or output of the vrho t compa r ator. conne ct extern al pull-u p . 29 ss/del controls con v erter softsta rt, power g o od, and over-curre nt dela y timing. co nne ct an external capa citor to l g nd to prog ram the timing . an optional resi sto r ca n b e adde d in se ri es with the ca pacito r to red u ce the ove r -curre nt delay time. 30 pwrgd open colle ct or output that drives lo w du ring softsta rt and any external fault con d ition. co nne ct externa l pull-up. 31 vidpgd open colle ct or output of the vccvi d powe r goo d ci rcuit r y. conn ect external p u ll- up. 32 viddel con n e c t an e x ternal ca pa citor to lgnd to prog ram th e vccvid po wer good d e l a y page 6 of 41 9 /30/04
ir3080 syst em theory of operat ion xphase tm ar chitec ture the xphas e tm architectu re is de signe d for multipha se interle a ved buck convert e rs whi c h a r e used i n appl ication s requi rin g sm all si ze, de si gn flexibility, low voltage, high cu rrent and fa st tran sient respon se. the a r chitecture ca n control converters of any pha se number where flexibility fa cilitates the desi gn trade-off of multiphase converters. the scala b le architectu re can be ap plied to other appli c ation s which requi re hig h curre n t or mu ltiple output voltage s. as sho w n i n figure 1, th e xphase tm archite c ture co nsi s ts of a control i c a nd a scal able array of ph ase converte rs each usin g a single pha s e ic. the co ntrol ic com m unicates with the phase ics throug h a 5-wire anal o g bus, i.e. bias voltage, pha se timin g , avera ge cu rr ent, erro r am plifier o u tput, and vid volta ge. th e cont rol ic in co rpo r ates al l the system functio n s, i.e. vid, pwm ramp oscillato r, erro r ampli f ier, bias voltage, and faul t protection s etc. th e phase i c imp l ements th e functio n s req u i r ed by the co nverter of e a c h ph ase, i. e. the gate driv ers, p w m co mparator and latch, over-volta ge protection, an d curre n t sen s i ng and sha r in g. there is no unu sed o r re dund ant silicon with the xphase tm archite c ture co mpared to others su ch a s a 4 phase controlle r tha t can be con f igured for 2, 3, or 4 ph a s e o p e r ation. pcb layo u t is e a si er sin c e the 5 wire bu s eliminate s the need for p o int-to-point wirin g betwe en the control ic and ea ch pha s e. the criti c al ga te drive an d curre n t sen s e conn ectio n s are sho r t and local to the phas e ics. this improv es the pcb layout by lowering th e para s itic in du ctan ce of the gate drive ci rcuits a nd re d u cin g the noi se of the cu rrent sen s e sig nal. 0. 1uf rc s ccs ci n 0. 1uf rc s ccs vo u t + 12 v v o ut s e ns e - vo u t - vi d 3 vi d 0 vi d 4 v o ut s e ns e + vi d 2 v c c p w rg d vr h o t vi d 1 vi d 5 >> bias vol tage >> vid volt age << curr ent sens e cu rren t sh are >> phas e ti ming ad di tio na l ph as es co ut ir 308 0 co ntr ol ic >> pwm cont rol cu rren t sh are inp ut /ou tp ut ir 308 6 ph ase ic co ntr ol bu s ir 308 6 ph ase ic vc c v i d (1. 2 v@150m a) vi d pw r g d 3. 3 v figure 1. system block di agra m page 7 of 41 9 /30/04
ir3080 pwm con t ro l method the pwm blo ck diag ram of the xphase tm architectu re is sho w n in f i gure 2. fee d - forward volta ge mo de cont rol with trailing ed ge modulatio n is used. a high -gain wide -ba ndwi d th voltage type error amplifier in the co ntrol ic is use d for the voltag e cont rol loo p . an external rc circuit co nne ct ed to th e input voltag e and g r ou nd is used to progra m the slop e of the pwm ram p and to provide the feed-forward co ntrol at each ph ase. the pwm ramp slope will chang e with the in put voltage an d automatically comp en sate f o r chan ge s in the input volt age. th e inp u t voltage ca n ch ang e due to variati ons in th e sil v er box outp u t voltage or due to wi re a nd pcb-t r ace voltage dro p related to ch ange s in load current. + - 10 k + - sh ar e ad ju s t er ro r a m p lif ie r cur re nt sen se amp li fie r x34 x 0 .91 2 0mv + - + - + - 10 k sh ar e ad ju s t er ro r a m p lif ie r cur re nt sen se amp li fie r x34 2 0mv x 0 .91 + - + - + - + - + - da ci n p w mr mp bi as i n ra m p i n - ra m p i n + ga t e h sc o m p i s ha re cs in + ga t e l ea i n cs i n - sy st em re fe ren ce vo lt age enab le clo ck pul se gen er ato r body brak ing comp arat or ram p dis ch arg e cla mp pw m la tc h s res et domin ant ph as e ic r pw m c omp ar ato r r drp rp w m rm p rp hs 2 cs co m p + - rp hs 1 + - + - rcs rv f b + - cp w m rm p cs co m p cc s rp w m rm p rcs + - cp w m rm p + - + - cc s rp hs 2 rp hs 1 + - gn d vo u t bi as i n vd ac vb i a s da ci n p w mr mp ra m p i n + vo s n s- vo s n s+ v o sn s- i s ha re ra m p i n - ii n vd r p ea i n ga t e h sc o m p cs i n - cs in + ga t e l ea o u t rm p o ut vi n fb ir os c sy st em re fe ren ce vo lt age vda c body brak ing comp arat or ram p dis ch arg e cla mp enab le clo ck pul se gen er ato r v bia s r egu la tor if b vdr p amp 50% dut y cyc le ra m p g e ne ra t o r vva lley vpe ak e rro r am p r s res et domin ant pw m la tc h ph as e ic cout co nt rol i c pw m c omp ar ato r figure 2. pwm block di agra m freque nc y a nd phase ti ming contro l the o scill ator is located in the co ntrol i c an d its fre q uen cy is p r og ramma ble fro m 150 khz to 1mhz by an external resi sto r . the output of th e oscillato r i s a 5 0 % dut y cycl e tri a n g le waveform with p e a k and valley voltages of approximatel y 5v and 1v respe c tively. this si gnal i s used to p r ogra m both t he switchi ng freque ncy a n d pha se timing of the phase ics. t he pha s e i c i s p r og ramm e d by re si stor divider r phs1 and r phs2 conne cted bet wee n the vbias refere nce volta ge a nd the ph ase ic lg nd pi n. a co mp ara t or in the p h ase i c s dete c ts the cro ssi ng of the oscillator wav e form over th e voltage gen er ated by the resi sto r divid e r and tri gge rs a clo c k pul se that starts t he pwm cycle. the p eak an d valle y voltages track the vbias vo ltage red u cin g potenti a l phase ic timing errors. figure 3 sho w s the p hase timing for a n 8 pha se converte r. note th at bot h sl ope s of t he tria ngle waveform ca n be u s ed for pha se timing by swa ppin g the rmpin+ a nd rmpin? p i ns, as sho w n in figure 2. page 8 of 41 9 /30/04
ir3080 ramp (from control ic) clk1 vvalle y (1.00v) phase ic clock pulses vph ase1&8 (1.5v) vph ase3&6 (3.5v) vph ase2&7 (2.5v) vph ase4&5 (4.5v) vpeak (5.0 v) clk2 50% ramp duty cycle clk3 clk4 clk5 clk6 clk7 clk8 slope = 80mv / % dc slope = 1.6mv / ns @ 200khz slope = 8.0mv / ns @ 1mhz figure 3. 8 phase oscillator waveform s pwm oper ation the p w m co mparator i s lo cated in the phase ic. upo n re ceivin g a clo c k pul se, t he pwm latch is set; the p w m r m p voltage begi ns to increase; the low side driver i s turned off, and the high side dri v er is then turned on after the non- overlap time. when the p w m r mp voltage exceed s the error a m plifier? s out put voltage, the pwm latch is re set. this turns off the high sid e driver an d then turn s on the lo w sid e driver after th e non-overla p time; it activates the ramp di scha rge cla m p, which qui ckly discha rge s th e pw m r mp cap a cito r to t he vda c vol t age of th e control i c until the next clo ck p u lse. the pwm lat c h is reset dominant allo wi ng all pha se s to go to zero duty cycle wi thin a few tens of nano se cond s in respon se to a load step decrea s e. ph ase s can overlap and go to 100% d u ty cycle in re spo n se to a load ste p increa se with turn -on gate d by the clo c k pul se s. an erro r amplifie r outp u t volta ge g r eate r th an the co mm on mo de input range o f the pwm compa r ator re sults i n 10 0 % duty cycle reg a rdl e ss o f the voltage of the pwm ramp. thi s arrang ement guarantee s the erro r amp lifier is always in cont rol a nd ca n dema nd 0 to 100% duty cycle as req u ire d . i t also f a v o r s re sp on se t o a loa d st ep d e cr ea se w h ic h is a ppropri a te given the low o u tput t o inp u t voltag e ratio of most sy stems. the inducto r current will in cre a se mu ch more rapidly than de crea se in resp on se to load tran sie n ts. this control method is de sign ed to p r o v ide ?sin gle cycle tran sient re sp on se? where the ind u c tor current chang es in respon se to l oad tra n sie n t s within a si ngle switchin g cycle m a ximizing th e effectivene ss o f the powe r train a n d minimizi ng th e output cap a citor re quire ments. an a dditional advantage of the archite c ture is that diff eren ce s i n grou nd o r inp u t voltage at the pha se s ha ve no effect on operation si nce the p w m ramp s are re feren c ed to v d ac. figure 4 depi cts pwm o p e r ating wavefo rms u nde r variou s co nditio n s. page 9 of 41 9 /30/04
ir3080 ph ase i c cl ock pu lse eai n vda c pw mrm p ga teh ga tel s tea dy -st at e o per at ion d uty c y c le in cre as e d ue to l oad i ncr ea se d uty c ycl e dec re as e d ue to vi n inc re as e ( fee d- for wa rd) d u t y c y c l e de cr eas e due t o loa d d e c rea se ( bod y bra ki ng) o r fau lt ( v c c u v , v ccv id uv , ocp , vi d=1 11 11x ) st ea dy- st ate op er ati on 91 % v d a c figure 4. pwm op eratin g wavefo rms body braking tm in a conventi onal syn c h r o nou s buck co nver ter, the minimum time requi red to redu ce the current in the indu ctor in respon se to a load step d e c re ase is; o min max slew v i i l t ) ( * the sl ew rate of the ind u ctor cu rrent can be sig n i ficantly incre a se d by turn ing off the synchrono us rectifier in respon se to a loa d step decrea s e. th e switch n o d e vo ltage is then fo rced t o de cr ea se until cond ucti on of th e synchro nou s re ctifier?s bo dy diode occu rs. t h is i n creases th e vo ltage a c ro ss the indu ctor from vout to vout + v bod y di ode . the minimu m time requi re d to red u ce the cu rre nt in the indu ct or in respon se to a lo ad transi ent decrea s e i s n o w; bodydiode o min max slew v v i i l t ) ( * since th e vol t age d r op i n t he bo dy dio d e is often hi g her th an o u tp ut voltage, th e indu cto r cu rre nt sle w rat e can be increa sed by 2x or more. this patent pendi ng te ch nique i s refe rre d to a s ?b ody braki ng? and i s a c co mplish e d throug h the ?0% duty cy cl e co mpa r ato r ? lo cated i n th e ph a s e ic. if the error a m plifier?s outp u t voltage drop s bel ow 91% of the vdac voltage this co mpa r at or turn s off the low si de gat e driver. lossles s av erage indu ctor curre nt s e nsing inducto r current ca n be se nse d by conn ecting a serie s resi st or and a ca pa citor n e twork in pa rallel with th e i ndu ctor and mea s u r in g the voltage across the ca pacito r , as sh own in fig u re 5. the equati on of the sen s ing n e two r k i s , cs cs l l cs cs l c c sr sl r s i c sr s v s v 1 ) ( 1 1 ) ( ) ( usually the resi stor rcs a nd capa citor ccs a r e cho s en so that th e time con s tant of rcs a nd ccs eq ual s the tim e con s tant of the in du ctor whi c h i s th e indu ctan ce l over the i n d u ctor dcr. if the two tim e con s tants match, th e voltage a c ro ss ccs is prop ortional to th e cu rrent thro ugh l, a nd th e se nse ci rcu i t can b e tre a t ed as if o n ly a se nse resi sto r with the value of r l was u s ed . the mi smat ch of the tim e const ants doe s not affect the m e a s u r eme n t of indu ctor dc current, but affects the a c compon ent of the indu ctor current. page 1 0 of 41 9 /30/04
ir3080 v l l r l i v l o r c cs cs c o cu rren t v s c c sense a m p csout figure 5. in ducto r cu rren t sensing an d current sen s e amplifier the advanta ge of sen s in g the indu cto r cu rre nt versu s high side or low si de sen s in g is th at actual out put curre n t being delive r ed to the load is obtaine d rather than pea k or sa m p led inform ation about the switch cu rre nts. the output voltag e ca n be po si tioned to m e et a load line based o n re al time inform ation. except for a sen s e resi stor i n seri es with th e indu cto r , this is the o n ly sen s e meth od that can suppo rt a sing le cy cl e tra n sient re sp on se . othe r method s provide no inform ation duri ng e i t her load in crease (lo w sid e sen s in g) o r load de crea se (high side sensi ng). an additional proble m associate d with pea k or valle y current mo de co ntrol for voltage posit ioning i s that they suffer from pea k-to -averag e erro rs. the s e e r rors will sh ow in many wa ys but one e x ample is th e effect of freque ncy variation. if the freq uen cy of a particul a r unit is 10 % low, the p eak to p e a k indu ctor curre n t will be 10 % large r and the output im peda nce of the c onverte r will drop by about 1 0 %. variation s in indu ctan ce, current sen s e amplifie r band width, p w m pro p d e l a y, any ad de d sl ope com pen sa tion, i n put voltage, and output v o ltage are all additio nal sou r ces of pe ak-to - ave r ag e errors. current sense amplifier a high sp eed differential cu rre nt sen s e a m plifier is lo cated in the p hase ic, as shown in figu re 5. its gain d e crea se s with in cre a si ng temp eratu r e a nd i s no minally 34 at 25oc an d 29 at 125o c (-1 470 p p m/oc). this red u cti on of ga i n tends to co m pen sate the 3850 ppm/o c increa se in i ndu ctor dcr. since in m o st de sign s th e phase ic j unctio n is hotter than th e indu ctors th ese t w o effe cts tend to ca ncel su ch th a t no addition a l temperature comp en satio n of the load line i s re quire d. the cu rrent sen s e amplifi e r ca n a c cep t positive differ ential inp u t up to 1 00m v and ne gati v e up to -20 m v befo r e clippi ng. the output of the curre n t se nse amplifier i s su mmed with the da c volta ge and se nt to the co ntrol ic and other pha s e s throug h an o n -chip 1 0 k ? resi sto r co nn ected to the i s hare pi n. the ishare pins of all the phase s are tie d toget her and th e voltage o n the sha r e bu s re pre s ent s the averag e current thro ugh a ll the indu cto r s an d is use d by the control ic for voltage posit i oning a nd current limit prot ection. av erage cur r ent shar e l oop curre n t sh ari ng bet wee n p hases of the conve r ter i s a c hiev e d by th e avera ge cu rre nt sh are l o op in e a ch phase ic. the o u tput of the current sense am plifie r is compa r ed with the share bu s le ss a 20mv offset. if current in a pha se i s smalle r tha n the average current, the sh are a d ju st am plifier of the p hase will acti vate a cu rren t sou r ce that redu ce s the slope of i t s pwm ram p thereby in crea sing its d u ty cy cle and output curre n t. the cro ssover freq uen cy of the curre n t share loop can be prog ram m ed with a capa ci tor at th e scomp pin so t hat the sh are loop do es no t intera ct with the outp u t voltage loo p . page 1 1 of 41 9 /30/04
ir3080 ir3080 theory of operati o n block diagra m the block dia g ram of the ir30 80 is sho w n in figu re 6, and sp ecifi c features a r e discusse d in the followin g se ction s . + - + - + - + - + - + - + - + - + - + - + - + - + - 8.9v + - + - + - + - + - + + - + - bbfb vosns- iin ocset vid3 vid5 vcc vidfb vrhot vid2 vid4 rmpout vdrp rosc vidpwr ss/del vid1 vidpgd pwrgd vbias vid0 hotset vdac lgnd fb eaout vccvid viddel irosc irosc vbias irosc irosc irosc irosc irosc i r o s c irosc irosc irosc irosc irosc disable vrhot comparator 6ua 50% duty cycle vccvid comparator discharge comparator + vid control vid = 11111x on idischg voltage proportional to absolute temperature over current current source generator 1.0v vccvid regulator fault latch + r start iocset 70ua ramp generator 6.85v 66ua start stop over-current comparator ss/del discharge ifb 4v 9.1v - ivttdel softstart clamp 5.0v s set dominant stop vbias regulator vdrp amp ichg rosc buffer amp vcc uvlo comparator 0.2v 1.1v - vid delay comparator off delay comparator 90mv 1.3v vid step-down vid dac output error amp 1.2v figure 6. ir3080 blo ck diagra m vid cont rol a 6-bit vid v o ltage comp a t ible with v r 10, a s sho w n in ta ble 1, is availa ble at the vda c pin. a detail ed blo c k diagram of th e vid co ntrol circuitry can be foun d in f i gure 7. the vid pins are internally p u ll ed up to vidpwr pin throug h 700 ? re si stors. t he vid inp u t comp arator s, with 0.6v ref e ren c e, monit o r th e vid pi ns and control the 6 bit digital-to -ana log conve r te r (dac) who s e output i s sent to the vdac buffer amplifie r. t he o u tput of the b u ffer amplifier i s th e vda c pin. the v d ac v o ltage i s p o st -pa c k age tri mmed to co mpen sate fo r the inp u t offsets of th e erro r amplifi e r to provide a 0.5% s y stem se t-poin t accu ra cy. t he a c tual v d ac voltage d oes not d e termine the system a c curacy and h a s a wide r tolera nce. page 1 2 of 41 9 /30/04
ir3080 the i r 30 80 can a c cept chang es in th e vid co de while op erati ng a nd va ry the da c volt age acco rdin gly. th e sin k /so u rce capability of the vdac bu ffe r amplifier is prog ram m ed by the same extern al resi stor th at sets the oscillator freq uen cy. the sl ew rate of the voltage at the vdac pin can be adj us te d by an external ca pa citor betwe en vdac pi n an d the vos n s- pin. a resi stor co nne cte d in se ri es with this cap a citor is re quire d to compe n s ate the vdac buffer amplifie r. di gital vid tra n sition s re sul t in a sm oot h an alog tra n sition of th e vda c volt age and conve r ter out put voltage minimizi ng in rush current s in the inp u t and o u tput capa citors an d overshoot of the output voltage. it is desi r able to prevent n egative indu ct or cu rrents i n re spo n se to a req u e s t for a lowe r vid cod e . neg a tive curren t transfo rm s th e bu ck co nverter i n to a b o o st conve r ter and tr a n sfe r s e n e r gy fro m the output cap a cito rs b a c k into the input voltage. this e n e r gy can ca use voltage spikes and d a mag e the silver box or othe r co mpone nts u n l e ss they are spe c ifical ly design ed t o handl e it. furthe rmo r e, p o we r is wa st ed du ring th e transfe r of e nergy from th e output back to the in put. the ir3 080 i n clu d e s ci rcu i try that turns off both con t rol and syn c hron ou s mo sfets in respon se to a lo wer vi d cod e so th at the load cu rre n t instead of the indu cto r di scharge s the output ca pa ci tors. a lower vid cod e is d e tected by the vid st ep-d o wn dete c t co mpa r ato r whi c h m onitors t he ?fa s t? output of the dac (plu s 7 m v for noi se immunity ) comp ared to the ?slo w? o u tput of the vdac pin. if a d y namic vid step do wn i s d e tected, the b ody brake lat c h i s set and the outp u t of the erro r amplifie r is pulled d o wn to 75% of the dac voltage by the vid body bra k e cla m p. thi s trigge rs the b ody braki n g tm function, which turns off both high sid e and lo w sid e drivers in th e pha se ics. the conve r te r?s output vol t age ne ed s t o be m onito red an d comp ared to the v d ac volta ge to determi ne whe n to resume no rm al operation. unfortu nately , the voltage on t he fb pin can be pull e d down by its compe n satio n netwo rk durin g the su dden de crea se in the error amplifier?s ou tput voltage so an additio n a l pin bbfb i s p r ovide d . t he bbfb pin is conn ected to the co nv erter outpu t voltage an d vdrp pin with re sisto r s o f the sa me v a lue a s on th e fb pin and th erefo r e provide s an u n -corru p t ed re presen tation of co nverter outp u t voltage. the reg u lation d e tect comp arator compa r e s the bbfb to the vdac voltag e and re se ts t he bo dy bra k e latch rele asing the e r ror amplifier? s output an d al lowin g no rma l ope ration to re sume. bo dy braki n g tm duri ng a t r a n sition to a l o we r vid co de can b e disa bled by conne cting the bbfb pin to grou nd. 700 + - 0. 6v vi d inp ut co mp ara to rs (1 o f 6 s how n) - di git al to an alo g co nve rt er + vd ac bu ffe r am p isink isource "f as t" vd ac vd ac " slo w" vd ac + - + - vi d d o w n bb cl am p 75% + - + - + - 7mv r eset d omin ant s 1 .7u s b lan ki ng re gu lat io n de te ct co mp ara to r r bod y bra ke lat ch vid s tep -d own det ec t com pa rat or 80 0ns bl ank in g ibb fb + - v i d = 11 111 x det ect enable ir osc ( fro m cur re nt so urc e gen era to r) t o e r r or am p vo sn s - bb f b vi d 3 vi d 5 ea o u t vi d 2 vi d 4 vi d 0 vi d 1 vi d p w r figure 7. vid co ntrol blo ck diag ram page 1 3 of 41 9 /30/04
ir3080 processo r pins (0 = low, 1 = high ) processo r pins (0 = low, 1 = high ) vid4 vid3 vid2 vid1 vid0 vid5 vout (v) vid4 vid3 vid2 vid1 vid0 vid5 vout (v) 0 1 0 1 0 0 0.837 5 1 1 0 1 0 0 1.212 5 0 1 0 0 1 1 0.850 0 1 1 0 0 1 1 1.225 0 0 1 0 0 1 0 0.862 5 1 1 0 0 1 0 1.237 5 0 1 0 0 0 1 0.875 0 1 1 0 0 0 1 1.250 0 0 1 0 0 0 0 0.887 5 1 1 0 0 0 0 1.262 5 0 0 1 1 1 1 0.900 0 1 0 1 1 1 1 1.275 0 0 0 1 1 1 0 0.912 5 1 0 1 1 1 0 1.287 5 0 0 1 1 0 1 0.925 0 1 0 1 1 0 1 1.300 0 0 0 1 1 0 0 0.937 5 1 0 1 1 0 0 1.312 5 0 0 1 0 1 1 0.950 0 1 0 1 0 1 1 1.325 0 0 0 1 0 1 0 0.962 5 1 0 1 0 1 0 1.337 5 0 0 1 0 0 1 0.975 0 1 0 1 0 0 1 1.350 0 0 0 1 0 0 0 0.987 5 1 0 1 0 0 0 1.362 5 0 0 0 1 1 1 1.000 0 1 0 0 1 1 1 1.375 0 0 0 0 1 1 0 1.012 5 1 0 0 1 1 0 1.387 5 0 0 0 1 0 1 1.025 0 1 0 0 1 0 1 1.400 0 0 0 0 1 0 0 1.037 5 1 0 0 1 0 0 1.412 5 0 0 0 0 1 1 1.050 0 1 0 0 0 1 1 1.425 0 0 0 0 0 1 0 1.062 5 1 0 0 0 1 0 1.437 5 0 0 0 0 0 1 1.075 0 1 0 0 0 0 1 1.450 0 0 0 0 0 0 0 1.087 5 1 0 0 0 0 0 1.462 5 1 1 1 1 1 1 of f 4 0 1 1 1 1 1 1.475 0 1 1 1 1 1 0 of f 4 0 1 1 1 1 0 1.487 5 1 1 1 1 0 1 1.100 0 0 1 1 1 0 1 1.500 0 1 1 1 1 0 0 1.112 5 0 1 1 1 0 0 1.512 5 1 1 1 0 1 1 1.125 0 0 1 1 0 1 1 1.525 0 1 1 1 0 1 0 1.137 5 0 1 1 0 1 0 1.537 5 1 1 1 0 0 1 1.150 0 0 1 1 0 0 1 1.550 0 1 1 1 0 0 0 1.162 5 0 1 1 0 0 0 1.562 5 1 1 0 1 1 1 1.175 0 0 1 0 1 1 1 1.575 0 1 1 0 1 1 0 1.187 5 0 1 0 1 1 0 1.587 5 1 1 0 1 0 1 1.200 0 0 1 0 1 0 1 1.600 0 note: 3. output disabled (fault mode ) table 1 - volt age identifica t ion (vid) adap tiv e voltage posi tioning adaptive voltage po sitioni ng i s n eed ed to red u ce the output volta g e deviatio n s durin g lo ad t r ansi ents an d the po we r dissipatio n of the load wh en it is drawi ng maximum curre n t. the circuitry relat ed to voltage positioni ng i s sho w n in figure 8. re sistor r fb i s conne cted bet wee n the e r ror amplifie r?s inve rting inp u t pin fb and the conve r te r?s output voltage. an i n ternal curre n t so urce wh ose value i s prog ra m m ed by the same external re si stor that p r o g rams th e oscillator freq uen cy pump s curre n t into t he fb pin. th e error amplif ier force s the conve r ter? s o u tput voltage lowe r to maintain a b a lan c e at its inputs. r fb is sele cted to prog ram th e desi r ed amo unt of fixed offset voltage belo w the dac voltage. the voltage a t the vdrp pi n is a b u ffere d versi on of t he share bu s and rep r e s en ts the sum of the dac volt age a nd the avera ge i ndu ctor curre n t of all the phases. th e vdrp pi n is conne cted to t he fb pin through the re si stor r drp . since the e r ror amplifie r will force th e lo op to maintai n fb to be e q ual to the v d ac refe ren c e voltage, an a dditiona l curre n t will fl ow into the fb pin e qual to (vdrp-v d ac) / r drp . when the l oad cu rre nt i n crea se s, th e ada ptive positio ning v o ltage in crea se s a c cordin gly. more cu rrent flo w s th rough th e fee dba ck re si sto r r fb , an d m a ke s the output voltag e lowe r prop ortional to th e load curren t. t he positio ning voltage can b e pro g rammed by th e resi sto r r drp so that the dro op i m peda nce p r o duces the de sire d co nvert e r output i m p edan ce. the offset an d slo pe of the conve r ter o u tput impeda nce are refere n c ed to an d therefo r e ind e p ende nt of the vdac voltag e. page 1 4 of 41 9 /30/04
ir3080 cs i n - cs i n + cs i n - v drp is ha re p h as e i c ea o u t p h as e i c c u r r ent s ens e a m p l if ie r is ha re is ha re is ha re is ha re ... .. . iin vd a c vd a c fb vd ac 10 k + - rfb + - r drp + - ifb 10 k + - vo er r o r a m p lif i e r c u r r ent s ens e a m p l if ie r c o n t r o l ic v drp a m p l if ie r cs i n + figure 8. adaptive voltage positio ning inductor dcr temper atu r e corr ectio n if the thermal compe n satio n of the inductor dcr pro v ided by the tempe r ature d epen dent gai n of the curre n t sen s e amplifier is n o t ade quate, a ne gative te m perature co efficient (nt c ) the r mi stor c an b e u s e d fo r a dditional correctio n . the thermist or sh ould b e place d clo s e to the indu ctor a nd con necte d in pa rallel with th e feedba ck resi stor, a s sho w n in fig u re 9. the re sisto r in se rie s with the the r mist o r is u s e d to redu ce the nonlin ea rity of the thermistor. a simila r netwo rk mu st be pl ace d on the bbfb pin to ensure p r o p e r ope ration d u ring a tran sition to a lowe r vid code with body brakin g tm . ea o u t iiniin er r o r a m p lif ie r c ont r o l i c av p am p l i f i e r + - rfb if b rf b 2 vd a c rdrp + - rt vo fb v drp figure 9. temperature co mpen sation o f inductor dcr remote voltage sensing to re du ce th e effect of im peda nce in th e gro und pla ne, the vos n s- pi n is u s ed for remote sen s in g and con n e c ted dire ctly to the load. the v d ac voltag e is refe re nced to vosn s- to avoid ad ditio nal erro r term s o r delay rel a ted to a sep a rate diff erential am pl ifier. the ca pacito r con n e ct ing the v d ac and v o sns- pin s ensure that high sp eed transi ents a r e fed directly into t he error amplifier with out delay. page 1 5 of 41 9 /30/04
ir3080 vcc vid lin ear re gulato r and vid pow e r good the ir3080 i n tegrate s a fu lly protecte d 1.2v/150ma vccvid li ne ar regul ator with over-cu r re nt prote c tion. powe r for the vccvid regul ator i s d r awn from th e vidpwr pi n whi c h is typically conn e c ted to a 3.3 v supply. if the linea r regul ator out put voltage i s above 1.1v for a time p e ri od p r og ramm ed by a capa cito r between viddel and lg nd, the vidpgd pin will send out a vid powe r good si gnal and st art-up of the converter i s allowed. the pwrgd pin i s an ope n-colle ctor out put an d sho u ld be p u lled up to a voltage so urce throug h a resi stor. an external npn tran sisto r can b e u s ed t o enha nce th e cu rre nt ca p ability of the linear reg u lato r, as sho w n i n figure 10. the 5 oh m resi sto r pro v ides loo p co mpen sation a nd over-cur re nt prote c tion. 1. 8 v 0. 1u f ir3 080 con trol ic v i dde l 3 2 vi d f b 1 vc c v i d 2 vi d p w r 3 vi d 5 4 vi d 0 5 vi d 1 6 vi d 2 7 vi d 3 8 pw r g d 3 0 trm1 10 trm2 11 vo sn s - 12 trm3 13 trm4 14 vd ac 16 ss / d el 2 9 vi d p g d 3 1 ro s c 15 vi d 4 9 v rho t 2 8 h o t set 2 7 rm p o u t 2 6 lg n d 2 5 vc c 2 4 vbi a s 2 3 bbf b 2 2 eao u t 2 1 fb 2 0 v drp 1 9 ii n 1 8 o c set 1 7 2. 5- 3 . 3v v ccv id vo u t se n s e - 1u f 5 oh m figure 10. vcc vid line a r regulato r u s i ng external transi s tor soft sta r t, o v er-current fault dela y , and hicc up mode the ir3080 has a p r og ra mmable soft-start fun c tion to lim it the surge cu rre nt durin g the conve r ter sta r t-up. a cap a cito r co n necte d betwe en the ss/del and lg nd pins controls soft start as well as ove r -current prote c t i on delay and hiccup mode timi ng. a ch arge cu rre nt of 7 0ua and di sch a rge curre n t of 6ua cont rol the up slo pe and do wn slop e of the voltage at the ss/del pin resp ectively figure 1 1 de picts the va ri ous op eratin g mode s as co ntrolle d by th e ss/del fun c tion. if there is n o fault, th e ss/del cap a cito r pin will begin to be cha r g ed. the error a m plif ier outp u t is clamp ed l o w until ss/del re ache s 1.3v. th e error amplifie r will then re gulate the co nverter? s out put vo ltage to match the ss/del voltage less the 1 . 3v offset until it re ache s the level d e t ermine d by t he vid i nput s. t he ss/del voltage conti nue s to in cre a se until it rises above 3.91v and all o ws the pwrgd si gnal to be asse rted. ss/del finally settles at 4v , indicating the end of the soft start. und e r voltag e lock out, a vid=11 111 x, and vcc vid faults immediately set the fault latch cau s ing s s /del to begin to di scharg e . the s s /del ca pa ci tor will contin ue to di sch arge do wn to 0 . 2v. if the fau l t has clea red the fault latch will be reset by the di scharge com parat or allowi ng a normal soft start to occur. a delay is in cluded if a n over-cu r rent co ndition o c curs afte r a su ccessful soft start se que nce. this i s requi red si nce over-cu r rent con d ition s ca n o c cur as p a rt of normal operation du e to lo ad tran sient s o r vid tran sition s. if an over- current fault occurs during nor mal operation it will initiate the discharge of the capacitor at ss/del but will not set the fault latch immediately. if the ov er-current con d ition persi sts lo ng enou gh fo r the ss/del capa citor to discha rg e below the 90mv offset of the delay co mparator, the fault latch will be set pu lling the error amplifier? s output low inhibiting switchin g in th e pha se ics an d de -a ssertin g the p w rg d signal. the ss/del cap a citor will co ntinue to discha rge u n til it reache s 0.2v and the fault latch is reset allo win g a normal soft start to occur. if an over-cu r rent con d ition i s a gain encount ered du ring the soft sta r t cycl e the fa ult latch will b e set witho u t any delay an d hi ccu p mode will be gin. du ring hi ccup mo de th e cha r g e to di scharge curre n t ratio re sult s in a fixed 7. 9% hiccup m ode duty cycle reg a rdl e ss of at wha t point the over-cu r rent co ndition o c curs. ho weve r, the hiccu p fre quen cy is d e termin ed b y the load curre n t and over-current set val ue. page 1 6 of 41 9 /30/04
ir3080 the ove r -cu r rent d e lay can b e redu ced by addin g a re si sto r in serie s wit h the ss/de l capa citor. the d e lay comp arator? s offset voltage is re du ced b y the d r op in t he resi stor caused by the discha rge current. th e val ue of th e seri es re sist o r sho u ld be 1 0 k ? or less to avoid interf erenc e with the s o ft s t art func tion. if ss/del pin is pulled b e lo w 0.9v, the converte r ca n be disabled. v idp gd (v ou t ch an ge s du e to l o a d an d vi d ch an ge s) oc p de la y oc p th re sh ol d 1. 3v vc c no rm al op er at io n st ar t- up po we r- do wn re -s ta rt af te r oc p h i c c u p ov er -c ur re nt pr ot ec ti on 1. 1v v idp wr 8. 9v uv lo ( 12v ) ( 3.3 v) v ccv id ( 1.2 v) v idd el 3. 91v 3. 91 v s s/d el p wrg d v out i out (v cc vi d ga te s fa ul t mo de ) (v cc g a t e s fa ul t mo de ) figure 11. operatin g wav e form s under volta g e locko ut (uvlo ) the uv lo fu nction m onito rs the i r 30 8 0 ?s vcc sup p ly pin and e n su re s that ir30 80 ha s a high en oug h voltage to power the int e rnal circuit. the ir30 80? s uvlo is se t higher than the minimum operat ing voltage of co mpatible phase ics th us providing uvlo p r ote c tion for them as well. du ri ng power- up the fault latch is re set wh en vcc excee d s 9.1 v and the r e is no other f ault. if the vcc volt a ge drop s b e lo w 8.9v the faul t latch will b e set. fo r conve r ters u s ing a sep a rate 5v supply f o r g a te d r iver bias an external uvlo ci rcuit ca n be adde d to p r e v ent any operation unti l adequ ate voltage is p r e s e n t. a diode co nne ct ed bet ween the 5v supply and the ss/del pin provide s a sim p le 5v uvlo fu nctio n . uvlo of the vidp wr i nput is p r ovided by th e v i d power go od fun c tion. adequa t e voltage must be pre s e n t at vidpwr pi n to allow vccvid to reach 1.1v. ov er current prote c tion (o cp) the current li mit threshold is set by a re sisto r conn ec ted betwe en t he ocset a nd vdac pin s . if the iin pin voltage, whi c h is p r o portion al to the avera ge curre n t plus da c voltage, exceed s the ocset voltage, the ove r -curre nt prote c tion is t r igge re d. page 1 7 of 41 9 /30/04
ir3080 vid = 1111 1 x fault vid cod e s of 1111 11 an d 1111 10 will set the fault latch an d di s abl e the error a m plifier. an 8 00n s delay is provide d to prevent a fault con d ition from oc cu rrin g durin g dyn a mic vid cha nge s. po w e r goo d outpu t the pwrg d pin is a n ope n-colle ctor o u t put and shou ld be pull ed u p to a voltage sou r ce thro u gh a resi stor. duri ng soft start, the pwrgd remain s low until the output vo ltage is in re gulatio n and ss/del is above 3.91v. th e pwrgd pi n become s lo w if the fault latch is set. a high leve l at t he pwrg d pin indi cate s that the conv erter i s in operation an d has n o fault, but does not ensu r e the output voltage is within the sp eci f ication. outp ut voltag e regul ation wit h in the de sig n limits can lo gically be a ssur ed h o wever, assu ming n o comp one nt failure in the system. load cu rren t indicator o u tpu t the vdrp pi n voltage rep r esents t he a v er age cu rre n t of the co n v erter pl us th e dac volta g e . the loa d current can be retri e ved b y a differential amplifier whi c h subt ra ct s the vdac volt age from the vdrp voltag e. sy stem refe rence voltag e (vbias ) the ir3 081 sup p lie s a 6.8v/5ma pre c i s ion referen c e volt age fro m the vbias pin. the oscillator ram p a m plitude tracks the vbias voltage, whi c h should be used to progra m the p hase ic tri p po ints to minimi ze ph ase del ay erro rs. thermal mo nitoring (v rhot ) the ir3 080 senses it s o w n die temp erature a nd p r o duces a volta ge at the in p u t of the vrhot com p a r ator that i s prop ortio nal to temperatu r e. an external resi stor di vi der conn ecte d from vbias to the hotset pin and ground can be u s e d to p r ogra m the th ermal trip poi nt of the v r ho t co mpa r ator. th e vrhot pin i s a n op en-coll ector outp u t and sh ould b e pulle d u p t o a voltag e source th ro ug h a re sisto r . if the therm a l trip p o int i s rea c he d the vrhot output drive s low. pulling hotset abov e approximat ely 7.5v will disabl e the oscillator (u se d d u ring fa ctory testing ) . page 1 8 of 41 9 /30/04
ir3080 application informations d bst rcs + c bst rp wm rm p cp wmrmp vgat e ro s c rv cc cv cc cv ccl rb b drp 20k rb ia s i n r p h ase62 rcs - r p h ase21 vi d d el 32 vi d f b 1 v ccv id 2 vi d p w r 3 vi d 5 4 vi d 0 5 vi d 1 6 vi d 2 7 vi d 3 8 pw r g d 30 trm1 10 trm2 11 vosn s- 12 trm3 13 trm4 14 vd ac 16 ss/ d e l 29 vi d p gd 31 ro s c 15 vi d 4 9 v rho t 28 ho ts e t 27 rmp o ut 26 lgn d 25 vc c 24 vbi as 23 bbf b 22 eaou t 21 fb 20 v drp 19 iin 18 oc set 17 ir3080 control ic r p h ase11 r p h ase33 20k rb ia s i n 1nf r p h ase42 cfb l rv cc rcs - d bst 20k rb ia s i n rcs + ccs + c bst ci n r p h ase43 r p h ase3 1 cv cc rcs - d bst ci n cdrp 0. 1uf cv cc rcs + cv ccl rcs + r p h ase12 ci n ci n cc p da cin 19 bi asi n 20 rm p i n+ 1 rm p i n- 2 gat e h 14 v cch 15 cs in- 17 ph sf lt 18 h o t set 3 v rho t 4 sc om p 6 eai n 7 pgn d 13 gat e l 12 lgn d 9 p w mrmp 8 is ha re 5 vc c 10 v ccl 11 cs in+ 16 i r3086 p hase ic cs co m p cs co m p ccs - rcs - r ss/ d e l cs co m p r p h ase41 da cin 19 bi asi n 20 rm p i n+ 1 rm p i n- 2 gat e h 14 v cch 15 cs in- 17 ph sf lt 18 h o t set 3 v rho t 4 sc om p 6 eai n 7 pgn d 13 gat e l 12 lgn d 9 p w mrmp 8 is ha re 5 vc c 10 v ccl 11 cs in+ 16 i r3086 p hase ic r bbf b rdrp l da cin 19 bi asi n 20 rm p i n+ 1 rm p i n- 2 gat e h 14 v cch 15 cs in- 17 ph sf lt 18 h o t set 3 v rho t 4 sc om p 6 eai n 7 pgn d 13 gat e l 12 lgn d 9 p w mrmp 8 is ha re 5 vc c 10 v ccl 11 cs in+ 16 i r3086 p hase ic rp ha s e 6 3 ccs - ci n 10 ohm rv cc ccs - ci n da cin 19 bi asi n 20 rm p i n+ 1 rm p i n- 2 gat e h 14 v cch 15 cs in- 17 ph sf lt 18 h o t set 3 v rho t 4 sc om p 6 eai n 7 pgn d 13 gat e l 12 lgn d 9 p w mrmp 8 is ha re 5 vc c 10 v ccl 11 cs in+ 16 i r3086 p hase ic cs co m p rs ha re rcs - rcp d bst rp wm rm p rv cc cv cc cp wmr m p c bst cv ccl ccs - rp wm rm p cp wmrm p ro cs e t r p h ase52 da cin 19 bi asi n 20 rm p i n+ 1 rm p i n- 2 gat e h 14 v cch 15 cs in- 17 ph sf lt 18 h o t set 3 v rho t 4 sc om p 6 eai n 7 pgn d 13 gat e l 12 lgn d 9 pw m r m p 8 is ha re 5 vc c 10 v ccl 11 cs in+ 16 i r3086 p hase ic rcs - rfb l c ss/ d e l cs co m p ccs + r p h ase22 cv da c 20k rb ia s i n ccs - r p h ase61 ccp 1 l ccs + r p h ase1 3 r p h ase53 ccs + l r p h ase23 da c i n 19 b i asi n 20 rm p i n+ 1 rm p i n- 2 gat e h 14 v cch 15 cs in- 17 ph s f l t 18 h o t set 3 v rho t 4 sc o m p 6 ea i n 7 pgn d 13 gat e l 12 lg n d 9 p w mrmp 8 is ha re 5 vc c 10 v ccl 11 cs in+ 16 i r3086 p hase ic rfb 1 20k rb ia s i n r p h ase32 ccs - cv idde l rv da c 0. 1 u f d bst rcs + l r p h ase51 20k rb ia s i n c bst ccs + ccs + cs co m p r drp 1 po w e r g o o d vo u t + vi d p g d v rho t vo u t sen se- vo u t sen se+ vi d 5 vo u t - vi d 3 vi d 4 vi d 0 vi d 2 vi d 1 12v rp wm rm p cp w m rmp distribution impedance cout rv cc cv cc cv ccl rp wm rm p cp wmrmp 1uf 3. 3v 0. 1u f rv cc cv cc cv ccl v ccv id rv cc cv cc cv ccl c bst rho t s e t c1 rho ts e t c2 rp wm rm p cp wmrmp d bst 3 rcs + c bst 2 rg a t e qgat e dg a t e figure 12. ir3080/ir308 6 six phase vrd 1 0 co nve r ter page 1 9 of 41 9 /30/04
ir3080 design procedures - ir3080 and ir3 086 chipset ir3080 external comp onents oscillator resistor ros c the oscillato r of ir308 0 g enerates a tri angle wavefo rm to syn c h r onize the p h a s e i c s, an d t he swit chin g freque ncy of the ea ch p hase conve r ter e qual s the oscillato r fr e quen cy, whi c h is set by th e extern al resistor r os c according t o the curve in f i gure 1 3 . vid delay c a pacit o r c vi ddel after the vid voltage of the integrate d lin ear regul ator is above 1.1v , there is a time delay bef ore the soft st art of the conve r ter i s initiated. the vid delay time t vid can be pro g ramm ed by an external cap a cit o r bet ween v i ddel pin and lg nd, and the ca pa ci tance i s determined by (1 ). 91 . 3 10 * 66 6 vid viddel t c (1) soft sta r t c a pacitor c ss/ del and resistor r ss/del b e cau s e t h e cap a cit o r c ss / d e l prog ra ms fou r different time pa ra meters, i.e. soft s t art delay time, s o ft s t art time, over-cu r rent l a tch d e lay ti me, and po wer g ood dela y time, they sho u ld b e co nsid ere d tog e ther whil e choo sing c ss/del . the ss/del pin voltage control s the sl ew rate of th e conv erte r o u tput voltage, as sho w n in figu re 11. a fter the viddel pin v o ltage ri se s a bove 3.91v, there i s a soft-sta r t delay time t ssdel, after whi c h the error am plifie r output is released to allow the so f t s t art. the soft s t art time t ss re present s the time du ring whi c h co nverter volta ge rises from z e ro to v o. t ss can be prog ram m e d by an external ca pa cito r, which is dete r mine d by equation (2 ). o ss o ss chg del ss v t v t i c * 10 * 70 * 6 / (2) once c ss/de l is cho s en, the soft start delay time t ssdel, the over-cu r rent fau l t latch delay time t ocdel , and the delay time t v ccpg from out put voltage (v o ) in re gula t ion to po we r goo d a r e fix ed a nd sh own in eq uation s (3), (4 ) and (5 ) re sp e c tively. 6 / / 10 * 70 3 . 1 * 3 . 1 * del ss chg del ss ssdel c i c t (3) 6 / / 10 * 6 09 . 0 * 09 . 0 * del ss dischg del ss ocdel c i c t (4) 6 / / 10 * 70 ) 3 . 1 91 . 3 ( * ) 3 . 1 91 . 3 ( * o del ss chg o del ss vccpg v c i v c t (5) if faster ove r -curre nt prot e c tion i s requi red, a re si stor in se rie s with the soft sta r t ca pa citor c ss/del can b e used to redu ce th e o v er-curre nt fault latch d e l a y time t o cdel , and the resi stor r ss/del is dete r mi ned by equa tion (6). equation (2) for soft sta r t cap a cito r c ss / d e l and eq uation (5) for powe r go od delay time t vccpg are un cha nge d, while the equ ation fo r soft start delay ti me t ss/del (equation 3) i s cha nge d to equatio n (7). con s id erin g the wo rst ca se value s o f charg e and discha rge cu rrent, r ss/del sho u ld not be greate r than 10 k . 6 / 6 / / 10 * 6 10 * 6 09 . 0 * 09 . 0 del ss ocdel dischg del ss dischg ocdel del ss c t i c i t r (6 ) page 2 0 of 41 9 /30/04
ir3080 6 6 / / / / 10 * 70 ) 10 * 70 3 . 1 ( * ) * 3 . 1 ( * del ss del ss chg chg del ss del ss ssdel r c i i r c t ( 7) vdac sle w rate progra mming capa citor c vdac and re sisto r r vdac the sl ew rat e of vdac d o wn -sl ope s r down can be programm ed by t he external ca pa citor c vdac a s defined in equation (8), whe r e i sink is the sin k current of vdac pin a s sh own in fi gure 15. the re sisto r r vdac is used to comp en sate vdac ci rcuit and is d e term ined by e quat ion (9 ). the sl ew rate of vdac up-slo pe sr up is pro p o rtional to that of vdac do wn-slo pe and i s giv en by equati on (1 0), where i sour ce is the sou r ce current of vdac pin a s s h ow n in f i gu r e 15 . down sink vdac sr i c (8) 2 15 10 2 . 3 5 . 0 vdac vdac c r (9) vdac source up c i sr (10) ov er current setting res i stor r o c set the inductor dc resi stance is utilized t o sense the i nductor current. the copper wi re of inductor has a constant temperature coeffici ent of 3850 p p m/ c , and therefo r e the maximu m indu ctor d cr can b e ca lculate d from equation ( 1 1) , w h er e r l_max and r l_room are the inductor dcr at maximum temperature t l_max and room te mperature t_ room res p ec tively. )] ( 10 * 3850 1 [ _ 6 _ _ room max l room l max l t t r r (11) the cu rre nt sen s e amplifi e r g a in of i r 30 86 d e cre a se s with te mperature at the rate of 1470 ppm/ c, which comp en sate s part of the inducto r dcr i n crea se. the phase ic di e temperatu r e is only a cou p le of degre e s cel s iu s highe r than th e pcb tempe r ature due to the low therm a l impeda nce of mlpq packag e . the mi nimum curren t sense amplifier g a in at the maximum pha se ic temperature t ic_max is ca lculate d from equation (12). )] ( 10 * 1470 1 [ _ 6 _ _ room max ic room cs min cs t t g g (12) the total in p u t offset voltage (v cs_tofst ) of curre n t sen s e am plifier in pha se ics i s th e su m of in put offset (v cs_ofs t) o f the amplifier itself and th at cr eate d by the amplifier input bias currents flo w in g throug h the current sen s e r e si st o r s r cs+ and r cs- . cs csin cs csin ofst cs tofst cs r i r i v v _ _ (13) the over cu rrent limit is se t by the external re si stor r o c set as defined in equ a tion (1 4), wh ere i limit is the requi re d over current l i mit. i o c set, the bia s curre n t of ocset pin, cha nge s with switchi n g frequ en cy setting resi st or r os c and is d e termined by the curve in fi g u re 1 4 . k p is the ratio of indu ctor p eak cu rrent ove r averag e cu rrent in eac h pha se an d is cal c ulate d fro m equation (15). ocset min cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1 ( [ _ _ _ (14) n i f v l v v v k o sw i o o i p / ) 2 /( ) ( (15) page 2 1 of 41 9 /30/04
ir3080 no load output voltag e setting resi stor r fb and adap tiv e voltage positio n ing resis t o r r drp a resi stor bet wee n fb pin and the conv erter out put i s u s ed to cre a te output vol t age offset v o_nl ofs t , which i s the differen c e b e t ween v dac voltage an d output voltag e at no lo ad con d it ion. a daptive volta ge po sitioni n g further lowe rs the co nverter voltag e by r o *i o, w here r o is the r e qu ir ed out put impeda nce of the conv erter. r fb is not on ly determine d by i fb , the current flowin g out of fb pin as sho w n in figure 14, bu t also affecte d by the adaptive volt age positio ni ng resi sto r r drp and total input off s et voltage of c u rr e n t s e ns e amp lifie rs . r fb and r drp are dete r min ed by (16 ) an d (17 ) re spe c tively, max l fb o tofst cs nlofst o max l fb r i r n v v r r _ _ _ _ (16) o min cs max l fb drp r n g r r r _ _ (17) con t rol ic o v er tempera t ure se tting resis t ors r hotset c1 and r ho tsetc2 the threshol d voltage of vrho t com parato r is pro portion al to th e die temp erature t j (o c) of control ic i r 30 80, as sho w n i n equ a tion (18). determin e the relation shi p b e tw ee n the di e tempe r atu r e of ir30 80 and the te mp eratu r e of the po we r co nverter a c cording to th e p o we r lo ss, pcb layout an d airflo w, et c. then calcula t e the vrho t thre sh ol d voltage co rre s po ndin g to the tempe r atu r e. 241 . 1 * 10 * 73 . 4 3 j vrhot t v (18) use vbias as the refe re nce volta ge. if r hotse t c1 is pre sele cted, r hotset c2 can be calcul ated a c cordin g to equation (19). vrhot vbias vrhot hotsetc hotsetc v v v r r 1 2 (19) body braking tm rela ted resis t ors r bbfb and r bb drp the bo dy brakin g tm durin g dynami c vid can b e di sabl ed by co nne cting bbfb pin to ground. if the feature i s enabl ed, re sistors r bbfb and r bbdrp are nee ded to resto r e t he feed ba ck voltage of the erro r am plifier afte r dynami c vid step do wn. usually r bbfb and r bbdrp are cho s en to match r fb a nd r drp res p ec tively . ir3086 external comp onents pwm ram p resis t or r pw mr mp and capa citor c p w mr mp pwm ram p is generated b y conne cting the resi stor r pwmrmp betwee n a volta ge sou r ce an d pwmrmp pin as well as th e cap a ci tor c pwmrmp between pwm r mp a n d lg nd. ch o o se the de sired p w m ram p mag n itude v pwmrmp and th e cap a citor c pwm r mp in the range of 1 0 0 p f an d 4 70p f, and t hen cal c ulate the re sisto r r p w mrmp from equation (20 ) . to achieve feed-fo rward voltage mod e control, the resi stor r ramp sho u ld be conne cted to t he input of the convert e r. )] ln( ) [ln( * * * pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r (20) inductor cur r ent sen s ing capaci tor c cs+ and resi stors r cs+ a nd r cs- the dc re sistance of the i ndu ctor i s util ized to se nse the indu cto r curre n t. usua lly the re sisto r r cs+ and capa citor c cs+ in pa ral l el with the in ducto r are ch ose n to match the time co nstant of the indu ct or, and therefore the voltage across the ca pacito r c cs+ rep r e s ent s the indu ctor current. if the two time con s ta nts are not the same, the ac comp one nt o f the capa cito r voltage i s d i fferent from t hat of the re al indu ctor cu rre nt. the tim e co nsta nt mismat ch doe s not affect the averag e curre n t sha r ing am ong th e multiple ph ase s , but affect the cu rre nt sign al ishare as well as the outp u t voltage duri n g the load current tran sie n t if adaptive voltage po sitioni ng is ad opted . page 2 2 of 41 9 /30/04
ir3080 measure the indu ctan ce l and the indu ctor dc re sist ance r l . pre-sele ct the ca pacito r c cs+ and calculate r cs+ as follows . cs l cs c r l r (21) the bia s current flowing o u t of the non -inverting in pu t of the curre n t sen s e a m p lifier create s a voltage d r o p acro ss r cs+, which i s eq uivalent t o an in put offset voltage of the cu rr ent sense amplifie r. the off s et affects the accuracy of conve r ter cu rrent si gnal i s hare a s well a s the accura cy of the co nverte r output voltage if adaptiv e voltage positio ning i s adopte d . to redu ce t he offset voltage, a re sisto r r cs- sh ould be ad ded b e twe en the amplifie r i n verting input and the conve r ter o u tput . the res i stor r cs- is de termine d by the ratio of the bias curre n t from the non -invertin g input and the bias curre n t from the inverti ng input. cs csin csin cs r i i r (22) if r cs- is not use d , r cs+ should be cho s en so that th e offset volta ge i s small e noug h. usu a l l y r cs+ sho u l d be le ss than 2 k an d therefo r e a large r c cs+ v a lue is n eed e d . ov er temperatur e settin g resis t ors r ho tset1 and r ho tset2 the th re shol d voltage of vrho t com parato r i s pro portion al to t he di e temp e r ature t j (o c) of ph ase ic. dete rmin e the relatio n sh ip between th e die tem perature of pha se ic an d the temperature of the po we r conve r ter accordin g to the po wer l o ss, p c b layo ut and ai rflo w etc, a nd th en ca lculate hotset th resh old voltag e co rrespon d i ng to the allowed maxi mum tempe r ature fro m equation (2 3). 241 . 1 * 10 * 73 . 4 3 j hotset t v (23) there a r e t w o ways to set the ove r tem peratu r e thre shol d, central setting and l o cal setting. in the cent ral setting, only one re si stor divide r is use d , and the setting vo ltage is co nn ected to ho tset pins of all the phase ics. to redu ce the inf l uen ce of noi se on the a c cura cy of over te mperatu r e setting, a 0.1 u f cap a cito r sho u ld be pla c ed n e xt to hotset p i n of ea ch ph ase i c . in the local setting, a re sisto r div i der p e r pha se is n eede d, and the settin g voltage is con n e c ted to ho tset pin of ea ch p hase. the 0. 1uf d e coupli ng cap a cito r i s n o t ne ce ssary. use vbias as th e referen c e voltage. if r hots et1 is pre-sel e cted, r ho tset2 can be ca lculate d as fol l ows. hotset bias hotset hotset hotset v v v r r 1 2 (24) phase dela y timing resistors r phase1 and r phase2 the ph ase d e lay of the i n terleave d m u ltipha se con v erte r i s pro g ramm ed by the re sisto r divider con necte d at rmpin+ o r rmpin- dep endin g on wh ich slop e of the o scill ator ramp is u s ed for the p h a s e delay p r og ra mming of pha se ic, as sho w n in fig u re 3. if the up slop e is u s ed, rmpin+ pin of the p h a s e i c sho u ld be con n e c ted to rmpo ut pi n of the cont rol ic an d rmpin- pin sho u ld b e co nne cted to t he resi stor d i vi der. when rmpo ut v o ltage i s ab o v e the trip v o ltage at rmpin- pin, the pwm latch is set. gat e l beco m e s lo w, and gat e h become s high after the non-overl ap time. if d o w n s l o p e is us ed , rmpin - p i n o f th e p h a s e ic s h ou ld b e c o nn ec te d to r m pou t p i n o f the c o n t r o l ic and rmpin+ pi n sho u ld be co nne cted to t he re sisto r d i vider. whe n rmp o ut v o ltage i s bel ow th e tri p v o ltage at rmpin- pin, the pwm latch is set. gat e l beco m e s lo w, and gat e h become s high after the non-overl ap time. use vbias voltage a s the refere nce for t he re sisto r divider sin c e the oscillato r ramp m agn itude from co ntrol ic tracks vbias voltage. try to avoid both edge s of the oscilla tor ra mp for bette r noise immuni ty. determine the rati o of the progra mming resi st ors correspon di ng to the de sire d switchin g frequ en cie s and p h a s e n u mbe r s. if the re sisto r r phasex 1 is pre- sel e ct e d , t he re sist o r r phasex 2 is determine d as: phasex phasex phasex phasex ra r ra r 1 1 2 (25) page 2 3 of 41 9 /30/04
ir3080 combined o v er tempera t ure an d pha se delay setting re sistor s r phase1 , r phase2 and r phase3 the over te mperature se tting re si stor divider can b e combi ned with the p h a s e delay re si stor divide r t o save one resi sto r per p hase. cal c ulate th e hotset th reshold volta ge v ho tset co rre sp ondi ng to the all o we d maxim u m tempe r at ure from equation (2 3). if the o v er temperature setting volt age is lowe r than the pha se d e lay setting voltage, vbias*ra phasex , conne ct rmpin+ or rmpin- pin betwe en r p h asex 1 and r phasex 2, an d conn ect hotset pin betwe en r phasex 2 and r p h asex 3 . pre-selec t r phase x 1 , ) 1 ( * ) ( 1 2 phasex bias phasex hotset bias phasex phasex ra v r v v ra r (26) ) 1 ( * 1 3 phasex bias phasex hotset phasex ra v r v r (27) if the over te mperature se tting voltage i s hi ghe r tha n the ph ase d e lay setting voltage, vbias*ra phasex , co nne ct hotset pin betwe en r ph asex 1 and r p h asex 2 and conne ct rmpi n+ o r rmpin- between r p h asex 2 and r phasex3 respec tively. pre-s e lec t r p h asex 1 , hotset bias phasex bias phasex hotset phasex v v r v ra v r 1 2 ) ( (28) hotset bias phasex bias phasex phasex v v r v ra r 1 3 * (29) boo t str a p capacitor c bst dep endin g o n the duty cy cle an d gate drive current of the pha se ic, a 0.1uf t o 1uf cap a ci tor is n eed ed for the bootstrap ci rcuit. deco upling capa citor s for phase ic 0.1uf-1uf de cou p ling cap a citors a r e re quire d at vcc and vccl pins of ph ase ics. voltage loop comp ensation the adaptive voltage posi tioning (avp) is usually adopted in the computer applications to i m prove the transient respon se and redu ce th e p o we r lo ss at heavy load. l i ke cu rre n t mode control, the ad aptive voltage p o sitio n ing loo p introdu ce s extra zero to th e voltage l o o p and splits t he do uble po les of th e p o w er sta ge, which ma ke th e voltage loop compe n s ation mu ch easi e r. re sist o r s r fb and r drp a r e cho s e n a c cording to eq uation s (16 ) and (17 ) , a n d the sele ction of comp en sa tion types depe nd s on the output ca pacito r s u s e d in the converter. fo r the applicatio ns using elect r olytic, polymer or al- polymer ca p a citors an d runnin g at lower freq uen cy, type ii comp ensation sho w n in figu re 17(a ) is u s ual ly enough. while for the appli c ations using only cerami c capacit o rs and runni ng at hi gher frequency, ty pe iii compensation sho w n in fig u re 17 (b ) is p r eferred. for a ppli c atio ns whe r e av p is not requi red, the com pen sati on i s t he same a s f o r the reg u lar voltage mod e co ntrol. for co nverte r usi n g polymer, al -polym er, a nd ce ra mic ca pa citors, which hav e mu ch hig h e r es r ze ro freque ncy, type iii comp ensation is re quire d as sho w n in figu re 17(b ) with r drp and c drp remov e d. t y pe ii compensa tion fo r avp applic ations determine th e com pen sati on at no loa d , the wo rst ca se condi tio n . cho o se the crossove r fre q uen cy fc bet wee n 1/10 and 1/5 of th e swit chin g freque ncy pe r pha se. assu me the time con s tant of the re si stor a nd ca pa citor across the output in du ctors mat c he s t hat of the ind u ctor, and de termine r cp and c cp fro m equatio ns (30 ) a nd (31 ) , whe r e l e and c e are t he e quivalen t indu ctan ce of output i n d u ctors and t he e quivalen t cap a cita nce of outp u t ca pacito r s r e spec tively. page 2 4 of 41 9 /30/04
ir3080 rc p cc p 1 eaou t cc p rf b rd rp vo+ v drp vd ac + - eaou t fbfb cfb cdrp rcp eao u t ccp 1 cc p rfb rd rp vo+ v drp vd ac fb + - eaou t rfb 1 (a) t y pe ii com pens atio n (b) t y pe iii compens ation figure 17. voltage loo p compen satio n netwo rk 2 2 ) * * * 2 ( 1 * ) 2 ( c c o pwmrmp fb e e c cp r c f v v r c l f r s s (30) cp e e cp r c l c 10 (31) c cp1 is optio nal and may be nee ded in some a ppli c a t ions to red u ce the jitter ca use d by the high frequ en cy noise. a cerami c ca pa citor bet wee n 10pf and 2 2 0pf is u s ually enoug h. t y pe iii com p ensation for avp applications determine th e com pen sati on at no lo a d , the wo rst ca se con d ition. assu me th e time co ns t ant of the re sisto r an d cap a cito r a c ross the outpu t inducto rs m a tche s th at of the ind u cto r , the cro s sover frequ en cy an d pha se ma rg in of th e voltage loop can b e estim a ted by equa tions (3 2) a n d (33), where r le is the eq uivalent re sist ance of indu ctor dcr. le fb cs e drp c r r g c r f * * 2 1 s (32) s t 180 ) 5 . 0 tan( 90 1 a c (33) cho o se the d e sired cro s so ver frequ en cy fc aro und fc1 es timate d b y equation (3 2) o r ch oo se fc between 1/ 10 an d 1/5 of the swi t ching freq ue ncy p e r pha se, and sele ct the comp o n e n ts to en sure the sl ope of close loop gai n is -2 0db /dec aro und the crossove r freque ncy. cho o se re si stor r fb1 a c cordin g to eq uation (34 ) , and d e termi n e c fb an d r drp from equation s (3 5) and (3 6). fb fb r r 2 1 1 to fb fb r r 3 2 1 (34) 1 4 1 fb c fb r f c s (35) drp fb fb fb drp r c r r c ) ( 1 (36) r cp an d c cp have limite d effect on the cro s sove r fre quen cy, and are used only to fine tun e t he cro s sove r freque ncy and tran sie n t load re sp on se. determi ne r cp and c cp from equatio ns (3 7) a nd (38). page 2 5 of 41 9 /30/04
ir3080 o pwmrmp fb e e c cp v v r c l f r 2 ) 2 ( s (37) cp e e cp r c l c 10 (38) c cp1 is optio nal and may be nee ded in some a ppli c a t ions to red u ce the jitter ca use d by the high frequ en cy noise. a cerami c ca pa citor bet wee n 10pf and 2 2 0pf is u s ually enoug h. t y pe iii com p ensation for non-avp applications re sist o r r fb is cho s en a c cordin g to eq u a tions (1 6), a nd resi stor r drp and capa citor c drp a r e not n eed ed. cho o se the cro s sover frequ en cy fc betwe en 1/1 0 and 1/5 of th e sw itching f r eque ncy p e r pha se and se lect the de sired p h a s e margi n c. calcul ate k factor from equa tion (39 ) , and determi n e the com pone nt values b a sed on equation s (4 0) t o (44 ) , )] 5 . 1 180 ( 4 tan[ c k t s (39) k v v f c l r r o pwmrmp c e e fb cp 2 ) 2 ( s (40) cp c cp r f k c s 2 (41) cp c cp r k f c s 2 1 1 (42) fb c fb r f k c s 2 (43) fb c fb c k f r s 2 1 1 (44) current s h are loop compens a tion the crossove r fre que ncy of the cu rrent s hare loo p sh o u ld b e at lea s t one de cad e lowe r th an th at of the volta ge lo op in orde r to eli m inate the in teractio n b e twee n the two loop s. a ca p a citor fro m s c omp to g r o und i s usuall y enou gh for the sha r e loop com p ensation. ch oose the cro s sover freq u ency of current sha r e lo op (f ci ) based on the cro s sove r fre quen cy of voltage loop (f c), and dete r min e the c sco m p , 6 _ 10 * 05 . 1 * 2 * )] ( * * * 2 1 [ * * * * * * 65 . 0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c s s (45) whe r e f mi is the pwm gai n in the curre n t share loop , ) ( * ) ( * * * dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f ( 46) page 2 6 of 41 9 /30/04
ir3080 design e x ample 1 - vrd 10 conve r t e r specifications input voltage : v i =12 v dac voltag e: v dac =1.35 v no lo ad out put voltage o ffset: v o_nlof st =20 mv output current: i o =105 a dc maximum output current: i oma x =120 a dc output imped ance: r o =0. 9 1 m vcc ready to vcc po wer good delay: t vccpg =0- 1 0 m s vid delay ti me: t vid =2. 5 ms soft start tim e : t ss =2ms over current delay: t ocde l =0. 5 ms dynami c vid do wn-sl ope slew rate: s r down = 2 .5mv/us over tem perature th re sh old: t pcb =11 5 oc power stage phase num b er: n=6 switchin g fre quen cy: f sw =400 khz output indu ctors: l = 22 0 n h , r l =0.47 m output ca pa citors: al-pol ymer, c=560 uf, r c = 7m , numbe r cn =10 ir3080 external comp onents oscillator resistor ros c once the switching frequ ency i s cho s en, r os c ca n be d e termi ned fro m the cu rve in fig u re 1 3 . fo r swit chin g freque ncy of 400 khz pe r p hase, cho o se r os c =30.1k vid delay c a pacit o r c vi ddel given vid de lay time t vid =2. 5 ms , the ca pacito r ca n is, nf t c vid viddel 42 91 . 3 10 * 5 . 2 10 * 66 91 . 3 * 10 * 66 3 6 6 , choo se 47 n f soft sta r t c a pacitor c ss/ del and resistor r ss/del bec a us e fast er ove r -cu r re nt prote c tion is requi re d, the soft sta r t ca pa citor c ss/del in series with the res i s t or r ss/del is used. cal c ulate the soft start cap a cito r fro m the requi re d soft start time. uf v t i c o ss chg del ss 1 . 0 10 * 20 35 . 1 10 * 2 10 * 70 3 3 6 / cal c ulate the soft start re si stor fro m the requi re d over current del ay time t ocdel , : k i c i t r dischg del ss dischg ocdel del ss 10 10 * 6 10 * 1 . 0 10 * 6 10 * 5 . 0 09 . 0 09 . 0 6 6 6 3 / / the s o ft s t art delay time is ms i i r c t chg chg del ss del ss ssdel 86 . 0 10 * 70 ) 10 * 70 * 10 * 10 3 . 1 ( 10 * 1 . 0 ) 3 . 1 ( 6 6 3 6 / / page 2 7 of 41 9 /30/04
ir3080 the po we r go od delay time is ms i v c t chg o del ss vccpg 8 . 1 10 * 70 ) 3 . 1 33 . 1 91 . 3 ( * 10 * 1 . 0 ) 3 . 1 91 . 3 ( * 6 6 / vdac sle w rate progra mming capa citor c vdac and re sisto r r vdac from fig u re 15, the sin k curre n t of vdac pin corresp ondi ng to 400khz (r os c =30.1 k ) i s 76ua. cal c ulate the vdac do wn -slop e sle w -ra t e prog rammi ng ca pa citor from the requi red do wn -slo pe sle w rate. nf sr i c down sink vdac 4 . 30 10 / 10 * 5 . 2 10 * 76 6 3 6 , choo se c vd ac =33n f cal c ulate the prog ram m ing resi stor. : 5 . 3 ) 10 * 33 ( 10 * 2 . 3 5 . 0 10 * 2 . 3 5 . 0 2 9 15 2 15 vdac vdac c r from fig u re 15, the sou r ce curre n t of vdac pin i s 11 0ua. the vdac up-slo pe sle w rate is us mv c i sr vdac source up / 3 . 3 10 * 33 10 * 110 9 6 ov er current setting res i stor r o c set the room te mperature is 25oc an d the target p c b t e mpe r at ure i s 1 00 o c . th e pha se ic di e tempe r atu r e is abo ut 1 oc high er tha n that of phase ic, and the indu ct or temp eratu r e is clo s e to pcb temperature. cal c ulate ind u ctor dc re si stan ce at 100 oc, : m t t r r room max l room l max l 61 . 0 )] 25 100 ( 10 * 3850 1 [ 10 * 47 . 0 )] ( 10 * 3850 1 [ 6 3 _ 6 _ _ the cu rrent sense amplifie r gain is 3 4 at 25oc, and its gain at 101o c is calculate d as, 2 . 30 )] 25 101 ( 10 * 1470 1 [ 34 )] ( 10 * 1470 1 [ 6 _ 6 _ _ room max ic room cs min cs t t g g set the over current limit at 135a. from fi gu re 1 4 , the bias curre n t of ocset pin (i o c set ) is 41ua with r os c =30.1 k . the total current sen s e amplifier inp u t offset volt ag e is 0.55 mv, whi c h i n cl ude s the offset created by the curre n t se nse am plifier input re sisto r mismat ch. cal c ulate con s tant k p, the ratio of induct o r pea k curre n t ov er avera ge cu rrent in each pha se, 3 . 0 6 / 135 ) 2 10 * 400 12 10 * 220 /( 33 . 1 ) 33 . 1 12 ( / ) 2 /( ) ( 3 9 n i f v l v v v k limit sw i o o i p ocset min cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1 ( [ _ _ _ : k 3 . 13 ) 10 * 41 /( 2 . 30 ) 10 * 55 . 0 3 . 1 10 * 61 . 0 6 135 ( 6 3 3 no load output voltag e setting resi stor r fb and adap tiv e voltage positio n ing resis t o r r drp from fig u re 14, the bias current of fb pin is 41ua wit h r os c =30.1 k . : 365 10 * 61 . 0 10 * 41 10 * 91 . 0 6 10 * 55 . 0 10 * 20 10 * 61 . 0 3 6 3 3 3 3 _ _ _ _ max l fb o tofst cs nlofst o max l fb r i r n v v r r page 2 8 of 41 9 /30/04
ir3080 : k r n g r r r o min cs max l fb drp 21 . 1 10 * 91 . 0 6 2 . 30 10 * 61 . 0 365 3 3 _ _ con t rol ic o v er tempera t ure se tting resis t ors r hotset c1 and r ho tsetc2 set the temperatu r e thre shold at 115 o c , whi c h corresp ond s to the ic die temperature of 116 oc. cal c ulate the hotset thre shol d voltage corre s po ndin g to the temperatu r e thre shold s . v t v j hotset 79 . 1 241 . 1 116 10 * 73 . 4 241 . 1 * 10 * 73 . 4 3 3 , choo se r h o tsetc1 =20.0k , : k v v v r r hotset bias hotset hotsetc hotsetc 15 . 7 79 . 1 8 . 6 79 . 1 10 * 20 3 1 2 bod y braking related re sistors r bbfb and r bbdr p n/a. the bod y brakin g du ri ng dynami c vid is disa ble d . ir3086 external comp onents pwm ram p resis t or r pw mr mp and capa citor c p w mr mp set pwm ramp magnitude v pwmrmp =0.8v. choo se 220 pf for pwm ramp capa citor c pw mrmp , and calcul ate the resi st o r r pw mrmp , )] ln( ) [ln( pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r : k 1 . 16 )] 8 . 0 35 . 1 12 ln( ) 35 . 1 12 [ln( 10 * 220 10 * 400 12 33 . 1 12 3 , choo se r p w mrmp =16.2 k inductor cur r ent sen s ing capaci tor c cs+ and resi stors r cs+ a nd r cs- cho o s e c cs+ =47 n f and calcul ate r cs+, : k c r l r cs l cs 0 . 10 10 * 47 ) 10 * 47 . 0 /( 10 * 220 9 3 9 the bia s cu rrents of csin+ and cs in- are 0.25 ua a nd 0.4ua re spec tively. cal c ulate resi sto r r cs- , : k r r cs cs 2 . 6 10 * 0 . 10 4 . 0 25 . 0 4 . 0 25 . 0 3 , choo se r cs- =6. 1 9 k ov er temperatur e settin g resis t ors r ho tset1 and r ho tset2 use cent ral o v er temp erature setting a nd set th e te mperat ure thresh old at 11 5 o c , which corre s p ond s the ic di e temperature of 116 oc. ca lculate the hotset thre shold voltage corre s p ondin g to the temperatu r e thre shold s . v t v j hotset 79 . 1 241 . 1 116 10 * 73 . 4 241 . 1 * 10 * 73 . 4 3 3 pre-s l ec t r h o tset1 =10.0 k , : k v v v r r hotset bias hotset hotset hotset 57 . 3 79 . 1 8 . 6 79 . 1 10 * 10 3 1 2 phase dela y timing resistors r phase1 and r phase2 use cent ral o v er temp erature setting a nd set th e te mperat ure thresh old at 11 5 o c , which corre s p ond s the ic di e temperature of 116 oc. ca lculate the hotset thre shold voltage corre s p ondin g to the temperatu r e thre shold s . page 2 9 of 41 9 /30/04
ir3080 the p h a s e d e lay re si stor ratio s fo r p hases 1 to 6 at 4 0 0 k hz of switching frequ en cie s are ra phas e1 = 0 .628, ra phase2 =0. 415, ra phas e3 = 0 .202, ra phase4 = 0 .246, ra phase5 =0.44 1 an d ra phase6 =0.6 37 sta r ting f r om do wn- slop e. pre-sel e ct r phase11 =r phase21 =r phase31 =r phase41 =r ph ase51 = r pha se61 =10 k , : k r ra ra r phase phase phase phase 9 . 16 10 * 10 628 . 0 1 628 . 0 1 3 11 1 1 12 r phase22 =7. 15k , r phas e32 =2. 5 5 k , r phase42 =3. 24k , p phase52 =7. 8 7 k , r phase62 = 17.4 k boo t str a p capacitor c bst cho o s e c bst =0. 1 u f deco upling capa citor s for phase ic and po w e r s t age cho o s e c vcc = 0 .1uf, c vccl =0.1uf voltage loop comp ensation type ii comp ensation i s u s ed fo r the co nverter with al-pol ymer o u tput ca pa citors. cho o se the cro s sover freque ncy fc=4 0khz, wh ich is 1/1 0 of the swit chin g freque ncy pe r phase, and d e termin e rcp and c cp . : k r c f v v r c l f r c c o ramp fb e e c cp 0 . 2 ) 10 * 7 * 10 * 560 * 10 * 40 * 2 ( 1 * ) 10 20 35 . 1 ( 8 . 0 365 ) 10 10 560 ( ) 6 / 10 220 ( ) 10 40 2 ( ) * * * 2 ( 1 * ) 2 ( 2 3 6 3 3 6 9 2 3 2 2 s s s s nf r c l c cp e e cp 71 10 0 . 2 ) 10 * 10 560 ( ) 6 / 10 220 ( 10 10 3 6 9 , choo se c cp =68 n f cho o s e c cp1 =47 p f to red u ce hi gh freq uen cy noise. current s h are loop compens a tion the cro s sove r frequ en cy of the current sha r e loo p f ci shoul d be at least one d e c ad e lower th an that of the voltage loop f c . choo se the cro s so ver frequ en cy of current sh are loo p f ci =4 kh z , a nd calculate c sco m p , 011 . 0 ) 35 . 1 12 ( * ) 35 . 1 8 . 0 12 ( 8 . 0 * 10 * 400 * 10 * 220 * 10 * 2 . 16 ) ( * ) ( * * * 3 12 3 dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10 * 05 . 1 * 2 * )] ( * * * 2 1 [ * * * * * * 65 . 0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c s s 6 3 4 4 6 3 3 3 10 * 05 . 1 * 10 * 4 2 ) 10 * 1 . 9 * 105 33 . 1 ( 011 . 0 * ] 105 ) 10 * 1 . 9 * 105 33 . 1 ( * 10 * 10 * 560 * 10 * 4 * 2 1 [ * ) 6 10 * 47 . 0 ( * 34 * 105 * 12 * 10 * 2 . 16 * 65 . 0 s s nf 4 . 31 cho o s e c sc o m p =33nf. page 3 0 of 41 9 /30/04
ir3080 design example 2 - evrd 10 high frequency all-ce ramic converte r specifications input voltage : v i =12 v dac voltag e: v dac = 1 .3 v no lo ad out put voltage o ffset: v o_nlof st =20 mv output current: i o =105 a dc maximum output current: i oma x =120 a dc output imped ance: r o =0. 9 1 m vcc ready to vcc po wer good delay: t vccpg =0- 1 0 m s vid delay ti me: t vid =2. 5 ms soft start tim e : t ss =2. 9 ms over current delay: t ocde l =2. 1 ms dynami c vid do wn-sl ope slew rate: s r down = 2 .5mv/us over tem perature th re sh old: t pcb =11 5 oc power stage phase num b er: n=6 switchin g fre quen cy: f sw =800 khz output indu ctors: l = 10 0 n h , r l =0.5 m output ca pa citors: ce ram i c, c=22uf, r c = 2m , nu mber cn =62 ir3080 external comp onents oscillator resistor ros c once the switching frequ ency i s cho s en, r os c ca n be d e termi ned fro m the cu rve in fig u re 1 3 . fo r swit chin g freque ncy of 800 khz pe r p hase, cho o se r os c =13.3k vid delay c a pacit o r c vi ddel given vid de lay time t vid =2. 5 ms , the ca pacito r ca n is, nf t c vid viddel 42 91 . 3 10 * 5 . 2 10 * 66 91 . 3 * 10 * 66 3 6 6 , choo se 47 n f soft sta r t c a pacitor c ss/ del and resistor r ss/del bec a us e fast er ove r -cu r re nt prote c tion is requi re d, the soft sta r t ca pa citor c ss/del in series with the res i s t or r ss/del is used. cal c ulate the soft start cap a cito r fro m the requi re d soft start time. uf v t i c o ss chg del ss 16 . 0 10 * 20 3 . 1 10 * 9 . 2 10 * 70 3 3 6 / , choo se c ss/ del =0.15uf cal c ulate the soft start re si stor fro m the requi re d over current del ay time t ocdel , : k i c i t r dischg del ss dischg ocdel del ss 1 10 * 6 10 * 15 . 0 10 * 6 10 * 1 . 2 09 . 0 09 . 0 6 6 6 3 / / the s o ft s t art delay time is ms i i r c t chg chg del ss del ss ssdel 6 . 2 10 * 70 ) 10 * 70 * 10 * 1 3 . 1 ( 10 * 15 . 0 ) 3 . 1 ( 6 6 3 6 / / page 3 1 of 41 9 /30/04
ir3080 the po we r go od delay time is ms i v c t chg o del ss vccpg 85 . 2 10 * 70 ) 3 . 1 28 . 1 91 . 3 ( * 10 * 15 . 0 ) 3 . 1 91 . 3 ( 6 6 / vdac sle w rate progra mming capa citor c vdac and re sisto r r vdac from figu re 15, the sin k curre n t of v d ac pin corresp ondi ng to 800 khz (r os c =13.3 k ) i s 1 70ua. cal c ulate the vdac do wn -slop e sle w -ra t e prog rammi ng ca pa citor from the requi red do wn -slo pe sle w rate. nf sr i c down sink vdac 68 10 / 10 * 5 . 2 10 * 170 6 3 6 cal c ulate the prog ram m ing resi stor. : 2 . 1 ) 10 * 68 ( 10 * 2 . 3 5 . 0 10 * 2 . 3 5 . 0 2 9 15 2 15 vdac vdac c r from fig u re 15, the sou r ce curre n t of vdac pin i s 25 0ua. the vdac up-slo pe sle w rate is us mv c i sr vdac source up / 7 . 3 10 * 68 10 * 250 9 6 ov er current setting res i stor r o c set the room te mperature is 25oc an d the target p c b t e mpe r at ure i s 1 00 o c . th e pha se ic di e tempe r atu r e is abo ut 1 oc high er tha n that of phase ic, and the indu ct or temp eratu r e is clo s e to pcb temperature. cal c ulate ind u ctor dc re si stan ce at 100 oc, : m t t r r room max l room l max l 64 . 0 )] 25 100 ( 10 * 3850 1 [ 10 * 5 . 0 )] ( 10 * 3850 1 [ 6 3 _ 6 _ _ the cu rrent sense amplifie r gain is 3 4 at 25oc, and its gain at 101o c is calculate d as, 2 . 30 )] 25 101 ( 10 * 1470 1 [ 34 )] ( 10 * 1470 1 [ 6 _ 6 _ _ room max ic room cs min cs t t g g set the over current limit at 135a. from fi gu re 1 4 , the bias curre n t of ocset pin (i o c set ) is 90ua with r os c =13.3 k . the total current sen s e amplifier inp u t offset volt ag e is 0.55 mv, whi c h i n cl ude s the offset created by the curre n t se nse am plifier input re sisto r mismat ch. cal c ulate con s tant k p, the ratio of induct o r pea k curre n t ov er avera ge cu rrent in each pha se, 32 . 0 6 / 135 ) 2 10 * 800 12 10 * 100 /( 28 . 1 ) 28 . 1 12 ( / ) 2 /( ) ( 3 9 n i f v l v v v k limit sw i o o i p ocset min cs tofst cs p max l limit ocset i g v k r n r r / ] ) 1 ( [ _ _ _ : k 34 . 6 ) 10 * 90 /( 2 . 30 * ) 10 * 55 . 0 32 . 1 10 * 64 . 0 6 135 ( 6 3 3 no load output voltag e setting resi stor r fb and adap tiv e voltage positio n ing resis t o r r drp from fig u re 14, the bias current of fb pin is 90ua wit h r os c =13.3 k . : 162 10 * 64 . 0 * 10 * 90 10 * 91 . 0 6 10 * 55 . 0 10 * 20 10 * 64 . 0 3 6 3 3 3 3 _ _ _ _ max l fb o tofst cs nlofst o max l fb r i r n v v r r page 3 2 of 41 9 /30/04
ir3080 : 576 10 * 91 . 0 6 2 . 30 * 10 * 64 . 0 162 3 3 _ _ o min cs max l fb drp r n g r r r con t rol ic o v er tempera t ure se tting resis t ors r hotset c1 and r ho tsetc2 set the temp eratu r e th re shold at 115 oc, which co rre sp ond s th e ic die tem peratu r e of 1 16 o c . calcu l ate the hotset thre shol d voltage corre s po ndin g to the temperatu r e thre shold s . v t v j hotset 79 . 1 241 . 1 116 10 * 73 . 4 241 . 1 * 10 * 73 . 4 3 3 , choo se r hotsetc1 =10.0k , : k v v v r r hotset bias hotset hotsetc hotsetc 57 . 3 79 . 1 8 . 6 79 . 1 10 * 10 3 1 2 bod y braking related re sistors r bbfb and r bbdr p n/a. the bod y brakin g du ri ng dynami c vid is disa ble d . ir3086 external comp onents pwm ram p resis t or r pw mr mp and capa citor c p w mr mp set pwm ra mp magnitu d e v pwmrmp =0.75v. choo se 100pf fo r pwm ram p capa citor c p w mrmp , and ca lculate the resi st o r r pw mrmp , )] ln( ) [ln( * * * pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r : k 2 . 18 )] 75 . 0 3 . 1 12 ln( ) 3 . 1 12 [ln( 12 10 * 100 3 10 * 800 12 28 . 1 inductor cur r ent sen s ing capaci tor c cs+ and resi stors r cs+ a nd r cs- cho o se 47nf for cap a cito r c cs+ and cal c ulate r cs+, : k c r l r cs l cs 22 . 4 10 * 47 ) 10 * 5 . 0 /( 10 * 100 9 3 9 the bia s cu rrents of csin+ and cs in- are 0.25 ua a nd 0.4ua re spec tively. cal c ulate resi sto r r cs- , : k r r cs cs 61 . 2 10 * 22 . 4 4 . 0 25 . 0 4 . 0 25 . 0 3 combined o v er tempera t ure an d pha se delay setting re sistor s r phasex1 , r phasex2 and r phasex3 the over tem peratu r e setting re sisto r di vider is co mb ined wi th the pha se delay resi stor divide r. set the temperatu r e threshold at 115 o c , whi c h corre s po nd s the ic die temper ature of 116 o c , a nd cal c ulate the hotset thre sh old voltage co rre s po ndin g to the tempe r atu r e thre sh old s . v t v j hotset 79 . 1 241 . 1 116 10 * 73 . 4 241 . 1 10 * 73 . 4 3 3 the p h a s e d e lay re si stor ratio s fo r p hases 1 to 6 at 8 0 0 k hz of switching frequ en cie s are ra phas e1 = 0 .665, ra phase2 =0. 432, ra phas e3 = 0 .198, ra phase4 = 0 .206, ra phase5 =0.40 1 an d ra phase6 =0.5 97 sta r ting f r om do wn- slop e. page 3 3 of 41 9 /30/04
ir3080 the over te mperature se tting voltage of phases 1, 2, 5, and 6 is lowe r tha n the pha se delay setting voltage, vbias*ra phasex . pre-selec t r phase11 =10 k , : k ra v r v v ra r phasex bias phasex hotset bias phasex phasex 1 . 12 ) 665 . 0 1 ( 8 . 6 10 * 10 ) 79 . 1 8 . 6 665 . 0 ( ) 1 ( * ) ( 3 1 2 : k ra v r v r phasex bias phasex hotset phasex 87 . 7 ) 665 . 0 1 ( * 8 . 6 10 * 1 . 12 79 . 1 ) 1 ( * 3 1 3 r phase21 = 10k , r phase22 =2. 9 4 k , r p h ase23 =4. 6 4 k r phase51 = 10k , r phase52 =2. 3 2 k , r p h ase53 =4. 4 2 k r phase61 = 10k , r phase62 =8. 2 5 k , r p h ase63 =6. 4 9 k the over tem peratu r e setting voltage of phase s 3 a n d 4 is highe r than the pha se delay setting voltage, vbias*ra phasex . pre-selec t r phasex1 =10 k , : 887 79 . 1 8 . 6 10 * 10 ) 8 . 6 198 . 0 79 . 1 ( ) ( 3 31 3 32 hotset bias phase bias phase hotset phase v v r v ra v r : k v v r v ra r hotset bias phase bias phase phase 67 . 2 79 . 1 8 . 6 10 * 10 8 . 6 198 . 0 * 3 31 3 33 r phase41 = 10k , r phase42 =76 8 , r pha se43 =2. 8 0 k boo t str a p capacitor c bst cho o s e c bst =0. 1 u f deco upling capa citor s for phase ic and po w e r s t age cho o s e c vcc = 0 .1uf, c vccl =0.1uf voltage loop comp ensation type iii compensation is used for the converter with only cerami c output capacitors. the crossover frequency and pha se ma rgin of the voltage loop can be estimated a s follows. khz r r g c r f le fb cs e drp c 146 ) 6 / 10 * 5 . 0 ( 162 34 ) 10 * 22 62 ( 2 576 2 3 6 1 s s q 63 180 ) 5 . 0 tan( 90 1 s t a c cho o s e : 110 162 3 2 3 2 1 fb fb r r cho o se the d e sired cro s so ver frequ en cy fc (=1 4 0 k hz) aroun d fc1 e s timated ab o v e, and cal c ul ate nf r f c fb c fb 2 . 5 110 10 * 140 4 1 4 1 3 1 s s , choo se c fb =5. 6 n f nf r c r r c drp fb fb fb drp 7 . 2 576 10 * 6 . 5 ) 110 162 ( ) ( 9 1 page 3 4 of 41 9 /30/04
ir3080 : k v v r c l f r o ramp fb e e c cp 65 . 1 10 * 20 3 . 1 75 . 0 * 162 ) 62 10 * 22 ( ) 6 / 10 * 100 ( ) 10 * 140 2 ( ) 2 ( 3 6 9 2 3 2 s s nf r c l c cp e e cp 27 10 65 . 1 ) 62 * 10 * 22 ( ) 6 / 10 * 100 ( 10 10 3 6 9 cho o s e c cp1 =47 p f to red u ce hi gh freq uen cy noise. current s h are loop compens a tion the cro s sove r frequ en cy of the current sha r e loo p f ci shoul d be at least one d e c ad e lower th an that of the voltage loop f c . choo se the cro s so ver frequ en cy of current sh are loo p f ci =3 . 5 kh z , a nd ca lculate c sco m p , 011 . 0 ) 3 . 1 12 ( * ) 3 . 1 75 . 0 12 ( 75 . 0 * 10 * 800 * 10 * 100 * 10 * 2 . 18 ) ( * ) ( * * * 3 12 3 dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10 * 05 . 1 * 2 * )] ( * * * 2 1 [ * * * * * * 65 . 0 ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c s s 6 4 4 6 3 3 10 * 05 . 1 * 3500 2 ) 10 * 1 . 9 * 105 33 . 1 ( 011 . 0 * ] 105 ) 10 * 1 . 9 * 105 33 . 1 ( * 62 * 10 * 22 * 3500 * 2 1 [ * ) 6 10 * 5 . 0 ( * 34 * 105 * 12 * 10 * 2 . 18 * 65 . 0 s s nf 6 . 20 cho o s e c sc o m p =22nf page 3 5 of 41 9 /30/04
ir3080 layout guidelines the followi ng layout guideli nes a r e reco mmend ed to redu ce the p a r asiti c indu cta n ce a nd re si stance of the pcb layout, therefore minimi zin g the noise couple d to the ic. x dedi cate at le ast one mid d l e layer for a g r oun d plan e l g nd. x con n e c t the grou nd tab u nder the cont rol ic to lg nd plan e throu gh a via. x place th e foll owin g critical comp one nts on the sa me l a yer a s cont rol ic a nd position them a s clo s e a s po ssible to the re spe c tive pins, r os c , r o c set , r vdac , c vda c , c vcc , c ss /del and r cc/del . avoid using any via for th e c o nn ec tio n . x place th e co mpen sation compon ents o n the sam e la yer a s cont rol ic a nd po sition them a s cl ose a s p o ssi b le to eaout, fb and vdrp pi n s . avoid usin g any via for the co nne ctio n. x use kelvin conne ction s fo r the remote voltage sen s e si g nal s, vo sns+ a nd v o sns-, a nd avoid cro s sin g over the fast tran si tion node s, i.e. switching n ode s, gate dri v e signal s an d bootst rap n ode s. x control bu s sign als, vda c , rmpo ut, iin, vbias, and e s p e ci a lly eaout, sho u ld n o t cross over th e fast transitio n nod es. page 3 6 of 41 9 /30/04
ir3080 pcb me tal a nd compon e n t placemen t x lead l and wi dth sh ould be equal to no minal pa rt lea d width. t h e minimum le a d to lead sp a c ing sh ould be ? 0.2mm t o minimize sh orting. x lead la nd len g th sho u ld be equal to max i mum part le a d length + 0. 2 mm outboa rd exten s ion + 0.05mm inboa rd exte nsio n. the o u tboard exte nsio n en sure s a large an d inspe c tabl e toe fillet, and the inboa rd extension will accommodat e any part mi salignment and ensure a fillet. x cente r p ad la nd len g th a n d width sh ould be e qual to maximum p a rt pad le ngth a nd wi dth. ho wever, th e minimum met a l to m e tal sp acin g sho u ld be ? 0.1 7 mm for 2 o z . cop per ( ? 0.1m m for 1 o z . cop per and ? 0.23mm for 3 oz. cop per) x a single 0.30 mm diamete r via shall be pl ace d in t he center of the p ad land a nd conne cted to g r oun d to minimize the noise effec t on the ic. page 3 7 of 41 9 /30/04
ir3080 solder resis t x the solde r re sist shoul d be pulled a w ay from the me t a l lead lan d s by a minimu m of 0.06mm. the sold er resi st mis-ali gnment is a maximum of 0.05mm and it is recom m ende d that the lead land s are all no n solder mask defined (ns m d). theref ore pulli ng the s/r 0.06m m will alwa y s ensure nsm d pads. x the mini mu m sol der re sist width i s 0.13mm, the r ef ore it is recom m en ded that the sol der re sist i s compl e tely re moved from betwe en the lead land s fo rming a si ngl e openin g for each ?g rou p ? of lead land s. x at the inside corne r of the sold er resi st whe r e the le a d land g r ou ps meet, it is re comm end ed to provid e a fillet so a solder resi st widt h of ? 0.17m m remain s. x the land p a d should b e solder ma sk defined (sm d ), with a minimum overla p of the solder resi st onto the cop p e r of 0.06mm to a c commo date sold er resi st mi s-alignm en t. in 0.5mm pitch cases it is allo wabl e to have the solder re sist o penin g for the land pad to b e smalle r tha n the part pa d. x ensu re that t he solde r re sist in-betwee n the le ad la nds and the pad la nd i s ? 0.15mm due to the hig h asp e ct ratio o f the solder re sist st rip sepa rating the lea d land s from the pad la nd. x the single via in the l and pad sho u ld b e tented with sold er re sist 0.4mm dia m e t er, or 0.1mm larg er tha n the diamete r of the via. page 3 8 of 41 9/ 3 0 / 0 4
ir3080 stencil de sign x the sten cil a pertu re s for t he lea d lan d s shoul d be approximatel y 80% of the are a of the lead la nd s. red u ci ng the amount of solder dep osit ed will mini mi ze the o c cu rrence of lead sho r ts. since for 0.5mm pitch devi c e s the lead s are only 0.25m m wide, t he sten cil ape rt ure s shoul d not be mad e narrower; openi ng s in stencil s < 0.25 mm wide a r e difficult to maintain rep eata b le sol der rel ease. x the sten cil le ad la nd a p e r ture s sho u ld t herefo r e be shorten ed i n le ngth by 80% and ce ntere d on the lea d land. x the la nd pa d ap ertu re sho u ld be striped with 0.25mm wid e op enin g s and sp aces to de po sit approximatel y 50% area of solder on th e cente r pad. if too much sold er is de p o sited on the center pa d the part will float and the le ad land s will be ope n. x the maximu m length and width of the land pad st encil a pertu re sho u ld be equal to the sold er resi st openi ng min u s an ann ular 0.2mm pull b a ck to de crea se t he i n ci de nce of sh ortin g the center l and to the lead lan d s wh en the part is pushed into t he sol der p a ste. page 3 9 of 41 9/ 3 0 / 0 4
ir3080 typical perform ance characte r istics fi gur e 13 - o s c i l l a t or f r equenc y ve r s us r o s c 15 0 20 0 25 0 30 0 35 0 40 0 45 0 50 0 55 0 60 0 65 0 70 0 75 0 80 0 85 0 90 0 95 0 10 00 10 15 2 0 25 3 0 3 5 40 4 5 50 55 6 0 65 7 0 75 80 8 5 90 95 1 0 0 ro s c ( k o h m s ) o s c i l l a t or fr e que nc y ( k h z ) f i g u re 1 4 - if b , b b f b , & oc s e t b i a s c u rr e n ts v s r o s c 5 15 25 35 45 55 65 75 85 95 10 5 11 5 12 5 10 15 20 2 5 30 35 40 4 5 50 5 5 60 65 7 0 7 5 80 85 9 0 95 1 0 0 ro s c ( k o h m ) ua fi g u r e 15 - v d a c s o u r ce & s i nk c u r r ent s vc r o s c ( i ncl udes o c s e t bi a s cur r e n t ) 0 25 50 75 10 0 12 5 15 0 17 5 20 0 22 5 25 0 27 5 30 0 32 5 10 2 0 30 4 0 50 60 70 80 90 100 110 120 130 14 0 r o s c ( k ohm ) ua is in k is o u r c e fi gu r e 1 6 - b i as c u r r e n t a ccur acy ve r s us r o sc ( i n c l u d e s t e m p er at ur e and i n put vol t a g e va r i a t i o n ) 0% 2% 4% 6% 8% 10 % 12 % 14 % 16 % 18 % 10 20 3 0 4 0 50 60 70 80 90 100 110 120 130 1 4 0 ro s c ( k o h m ) + / -3 s i g m a v a r i ati o n (% ) f b , bb f b , o c se t bi a s cu r r e n t v d a c s i nk c u rrent v d a c s ourc e c u rrent page 4 0 of 41 9/ 3 0 / 0 4
ir3080 package information 32l mlpq (5 x 5 mm body ) ?

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